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Apply clang-tidy modernize-use-nodiscard fixes

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This commit is contained in:
Derek Christ
2023-05-15 10:53:04 +02:00
parent 6f7ca94d27
commit 77decb70ec
24 changed files with 90 additions and 90 deletions
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48
src/libdramsys/DRAMSys/common/dramExtensions.h
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@@ -50,7 +50,7 @@ class Thread
public:
explicit Thread(unsigned int id) : id(id) {}
unsigned int ID() const
[[nodiscard]] unsigned int ID() const
{
return id;
}
@@ -64,7 +64,7 @@ class Channel
public:
explicit Channel(unsigned int id) : id(id) {}
unsigned int ID() const
[[nodiscard]] unsigned int ID() const
{
return id;
}
@@ -78,7 +78,7 @@ class Rank
public:
explicit Rank(unsigned int id) : id(id) {}
unsigned int ID() const
[[nodiscard]] unsigned int ID() const
{
return id;
}
@@ -92,7 +92,7 @@ class BankGroup
public:
explicit BankGroup(unsigned int id) : id(id) {}
unsigned int ID() const
[[nodiscard]] unsigned int ID() const
{
return id;
}
@@ -106,12 +106,12 @@ class Bank
public:
explicit Bank(unsigned int id) : id(id) {}
unsigned int ID() const
[[nodiscard]] unsigned int ID() const
{
return id;
}
std::string toString() const
[[nodiscard]] std::string toString() const
{
return std::to_string(id);
}
@@ -129,7 +129,7 @@ public:
explicit Row(unsigned int id) : id(id), isNoRow(false) {}
unsigned int ID() const
[[nodiscard]] unsigned int ID() const
{
return id;
}
@@ -148,7 +148,7 @@ class Column
public:
explicit Column(unsigned int id) : id(id) {}
unsigned int ID() const
[[nodiscard]] unsigned int ID() const
{
return id;
}
@@ -166,13 +166,13 @@ public:
static void setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, uint64_t threadPayloadID,
const sc_core::sc_time& timeOfGeneration);
tlm::tlm_extension_base* clone() const override;
[[nodiscard]] tlm::tlm_extension_base* clone() const override;
void copy_from(const tlm::tlm_extension_base& ext) override;
Thread getThread() const;
Channel getChannel() const;
uint64_t getThreadPayloadID() const;
sc_core::sc_time getTimeOfGeneration() const;
[[nodiscard]] Thread getThread() const;
[[nodiscard]] Channel getChannel() const;
[[nodiscard]] uint64_t getThreadPayloadID() const;
[[nodiscard]] sc_core::sc_time getTimeOfGeneration() const;
static const ArbiterExtension& getExtension(const tlm::tlm_generic_payload& trans);
static Thread getThread(const tlm::tlm_generic_payload& trans);
@@ -199,16 +199,16 @@ public:
//static ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans);
tlm::tlm_extension_base* clone() const override;
[[nodiscard]] tlm::tlm_extension_base* clone() const override;
void copy_from(const tlm::tlm_extension_base& ext) override;
uint64_t getChannelPayloadID() const;
Rank getRank() const;
BankGroup getBankGroup() const;
Bank getBank() const;
Row getRow() const;
Column getColumn() const;
unsigned getBurstLength() const;
[[nodiscard]] uint64_t getChannelPayloadID() const;
[[nodiscard]] Rank getRank() const;
[[nodiscard]] BankGroup getBankGroup() const;
[[nodiscard]] Bank getBank() const;
[[nodiscard]] Row getRow() const;
[[nodiscard]] Column getColumn() const;
[[nodiscard]] unsigned getBurstLength() const;
static const ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans);
static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload& trans);
@@ -264,7 +264,7 @@ private:
public:
//ChildExtension() = delete;
tlm::tlm_extension_base* clone() const override;
[[nodiscard]] tlm::tlm_extension_base* clone() const override;
void copy_from(const tlm::tlm_extension_base& ext) override;
tlm::tlm_generic_payload& getParentTrans();
static tlm::tlm_generic_payload& getParentTrans(tlm::tlm_generic_payload& childTrans);
@@ -283,7 +283,7 @@ private:
public:
ParentExtension() = delete;
tlm_extension_base* clone() const override;
[[nodiscard]] tlm_extension_base* clone() const override;
void copy_from(const tlm_extension_base& ext) override;
static void setExtension(tlm::tlm_generic_payload& parentTrans, std::vector<tlm::tlm_generic_payload*> childTranses);
const std::vector<tlm::tlm_generic_payload*>& getChildTranses();
@@ -294,7 +294,7 @@ public:
class EccExtension : public tlm::tlm_extension<EccExtension>
{
public:
tlm_extension_base* clone() const override
[[nodiscard]] tlm_extension_base* clone() const override
{
return new EccExtension;
}

6
src/libdramsys/DRAMSys/common/utils.h
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@@ -56,9 +56,9 @@ public:
TimeInterval() : start(sc_core::SC_ZERO_TIME), end(sc_core::SC_ZERO_TIME) {}
TimeInterval(const sc_core::sc_time& start, const sc_core::sc_time& end) : start(start), end(end) {}
sc_core::sc_time getLength() const;
bool timeIsInInterval(const sc_core::sc_time &time) const;
bool intersects(const TimeInterval &other) const;
[[nodiscard]] sc_core::sc_time getLength() const;
[[nodiscard]] bool timeIsInInterval(const sc_core::sc_time &time) const;
[[nodiscard]] bool intersects(const TimeInterval &other) const;
};
constexpr const char headline[] =

28
src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h
View File

@@ -86,25 +86,25 @@ public:
virtual ~MemSpec() = default;
virtual sc_core::sc_time getRefreshIntervalAB() const;
virtual sc_core::sc_time getRefreshIntervalPB() const;
virtual sc_core::sc_time getRefreshIntervalP2B() const;
virtual sc_core::sc_time getRefreshIntervalSB() const;
[[nodiscard]] virtual sc_core::sc_time getRefreshIntervalAB() const;
[[nodiscard]] virtual sc_core::sc_time getRefreshIntervalPB() const;
[[nodiscard]] virtual sc_core::sc_time getRefreshIntervalP2B() const;
[[nodiscard]] virtual sc_core::sc_time getRefreshIntervalSB() const;
virtual unsigned getPer2BankOffset() const;
[[nodiscard]] virtual unsigned getPer2BankOffset() const;
virtual unsigned getRAAIMT() const;
virtual unsigned getRAAMMT() const;
virtual unsigned getRAADEC() const;
[[nodiscard]] virtual unsigned getRAAIMT() const;
[[nodiscard]] virtual unsigned getRAAMMT() const;
[[nodiscard]] virtual unsigned getRAADEC() const;
virtual bool hasRasAndCasBus() const;
[[nodiscard]] virtual bool hasRasAndCasBus() const;
virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0;
virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0;
[[nodiscard]] virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0;
[[nodiscard]] virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0;
sc_core::sc_time getCommandLength(Command) const;
double getCommandLengthInCycles(Command) const;
uint64_t getSimMemSizeInBytes() const;
[[nodiscard]] sc_core::sc_time getCommandLength(Command) const;
[[nodiscard]] double getCommandLengthInCycles(Command) const;
[[nodiscard]] uint64_t getSimMemSizeInBytes() const;
protected:
MemSpec(const DRAMSys::Config::MemSpec& memSpec,

6
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h
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@@ -93,10 +93,10 @@ public:
const double iDD3P0;
const double iDD3P1;
sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

6
src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h
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@@ -100,10 +100,10 @@ public:
const double iDD62;
const double vDD2;
sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

8
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h
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@@ -90,11 +90,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

8
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h
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@@ -90,11 +90,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

12
src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h
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@@ -91,13 +91,13 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getRefreshIntervalP2B() const override;
unsigned getPer2BankOffset() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalP2B() const override;
[[nodiscard]] unsigned getPer2BankOffset() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
private:
unsigned per2BankOffset;

10
src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h
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@@ -85,13 +85,13 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
bool hasRasAndCasBus() const override;
[[nodiscard]] bool hasRasAndCasBus() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

8
src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h
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@@ -86,11 +86,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

4
src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h
View File

@@ -78,8 +78,8 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

6
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h
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@@ -98,10 +98,10 @@ public:
const double iDD62;
const double vDD2;
sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

8
src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h
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@@ -79,11 +79,11 @@ public:
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override;
[[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
[[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
};
} // namespace DRAMSys

2
src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h
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@@ -49,7 +49,7 @@ class CheckerDDR3 final : public CheckerIF
{
public:
explicit CheckerDDR3(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

2
src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h
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@@ -51,7 +51,7 @@ class CheckerDDR4 final : public CheckerIF
{
public:
explicit CheckerDDR4(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

2
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h
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@@ -49,7 +49,7 @@ class CheckerGDDR5 final : public CheckerIF
{
public:
explicit CheckerGDDR5(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

2
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h
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@@ -49,7 +49,7 @@ class CheckerGDDR5X final : public CheckerIF
{
public:
explicit CheckerGDDR5X(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

2
src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h
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@@ -49,7 +49,7 @@ class CheckerGDDR6 final : public CheckerIF
{
public:
explicit CheckerGDDR6(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

2
src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h
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@@ -49,7 +49,7 @@ class CheckerHBM2 final : public CheckerIF
{
public:
explicit CheckerHBM2(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

2
src/libdramsys/DRAMSys/controller/checker/CheckerIF.h
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@@ -47,7 +47,7 @@ class CheckerIF
public:
virtual ~CheckerIF() = default;
virtual sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const = 0;
[[nodiscard]] virtual sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const = 0;
virtual void insert(Command command, const tlm::tlm_generic_payload& payload) = 0;
};

2
src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h
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@@ -49,7 +49,7 @@ class CheckerLPDDR4 final : public CheckerIF
{
public:
explicit CheckerLPDDR4(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

2
src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h
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@@ -49,7 +49,7 @@ class CheckerSTTMRAM final : public CheckerIF
{
public:
explicit CheckerSTTMRAM(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

2
src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h
View File

@@ -49,7 +49,7 @@ class CheckerWideIO final : public CheckerIF
{
public:
explicit CheckerWideIO(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private:

2
src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h
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@@ -49,7 +49,7 @@ class CheckerWideIO2 final : public CheckerIF
{
public:
explicit CheckerWideIO2(const Configuration& config);
sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
[[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override;
void insert(Command command, const tlm::tlm_generic_payload& payload) override;
private: