From 77decb70ec55dc00c2ce92ea7cd656fc94019655 Mon Sep 17 00:00:00 2001 From: Derek Christ Date: Mon, 15 May 2023 10:53:04 +0200 Subject: [PATCH] Apply clang-tidy modernize-use-nodiscard fixes --- .../DRAMSys/common/dramExtensions.h | 48 +++++++++---------- src/libdramsys/DRAMSys/common/utils.h | 6 +-- .../DRAMSys/configuration/memspec/MemSpec.h | 28 +++++------ .../configuration/memspec/MemSpecDDR3.h | 6 +-- .../configuration/memspec/MemSpecDDR4.h | 6 +-- .../configuration/memspec/MemSpecGDDR5.h | 8 ++-- .../configuration/memspec/MemSpecGDDR5X.h | 8 ++-- .../configuration/memspec/MemSpecGDDR6.h | 12 ++--- .../configuration/memspec/MemSpecHBM2.h | 10 ++-- .../configuration/memspec/MemSpecLPDDR4.h | 8 ++-- .../configuration/memspec/MemSpecSTTMRAM.h | 4 +- .../configuration/memspec/MemSpecWideIO.h | 6 +-- .../configuration/memspec/MemSpecWideIO2.h | 8 ++-- .../DRAMSys/controller/checker/CheckerDDR3.h | 2 +- .../DRAMSys/controller/checker/CheckerDDR4.h | 2 +- .../DRAMSys/controller/checker/CheckerGDDR5.h | 2 +- .../controller/checker/CheckerGDDR5X.h | 2 +- .../DRAMSys/controller/checker/CheckerGDDR6.h | 2 +- .../DRAMSys/controller/checker/CheckerHBM2.h | 2 +- .../DRAMSys/controller/checker/CheckerIF.h | 2 +- .../controller/checker/CheckerLPDDR4.h | 2 +- .../controller/checker/CheckerSTTMRAM.h | 2 +- .../controller/checker/CheckerWideIO.h | 2 +- .../controller/checker/CheckerWideIO2.h | 2 +- 24 files changed, 90 insertions(+), 90 deletions(-) diff --git a/src/libdramsys/DRAMSys/common/dramExtensions.h b/src/libdramsys/DRAMSys/common/dramExtensions.h index 215785f8..2157bc06 100644 --- a/src/libdramsys/DRAMSys/common/dramExtensions.h +++ b/src/libdramsys/DRAMSys/common/dramExtensions.h @@ -50,7 +50,7 @@ class Thread public: explicit Thread(unsigned int id) : id(id) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } @@ -64,7 +64,7 @@ class Channel public: explicit Channel(unsigned int id) : id(id) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } @@ -78,7 +78,7 @@ class Rank public: explicit Rank(unsigned int id) : id(id) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } @@ -92,7 +92,7 @@ class BankGroup public: explicit BankGroup(unsigned int id) : id(id) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } @@ -106,12 +106,12 @@ class Bank public: explicit Bank(unsigned int id) : id(id) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } - std::string toString() const + [[nodiscard]] std::string toString() const { return std::to_string(id); } @@ -129,7 +129,7 @@ public: explicit Row(unsigned int id) : id(id), isNoRow(false) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } @@ -148,7 +148,7 @@ class Column public: explicit Column(unsigned int id) : id(id) {} - unsigned int ID() const + [[nodiscard]] unsigned int ID() const { return id; } @@ -166,13 +166,13 @@ public: static void setIDAndTimeOfGeneration(tlm::tlm_generic_payload& trans, uint64_t threadPayloadID, const sc_core::sc_time& timeOfGeneration); - tlm::tlm_extension_base* clone() const override; + [[nodiscard]] tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; - Thread getThread() const; - Channel getChannel() const; - uint64_t getThreadPayloadID() const; - sc_core::sc_time getTimeOfGeneration() const; + [[nodiscard]] Thread getThread() const; + [[nodiscard]] Channel getChannel() const; + [[nodiscard]] uint64_t getThreadPayloadID() const; + [[nodiscard]] sc_core::sc_time getTimeOfGeneration() const; static const ArbiterExtension& getExtension(const tlm::tlm_generic_payload& trans); static Thread getThread(const tlm::tlm_generic_payload& trans); @@ -199,16 +199,16 @@ public: //static ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans); - tlm::tlm_extension_base* clone() const override; + [[nodiscard]] tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; - uint64_t getChannelPayloadID() const; - Rank getRank() const; - BankGroup getBankGroup() const; - Bank getBank() const; - Row getRow() const; - Column getColumn() const; - unsigned getBurstLength() const; + [[nodiscard]] uint64_t getChannelPayloadID() const; + [[nodiscard]] Rank getRank() const; + [[nodiscard]] BankGroup getBankGroup() const; + [[nodiscard]] Bank getBank() const; + [[nodiscard]] Row getRow() const; + [[nodiscard]] Column getColumn() const; + [[nodiscard]] unsigned getBurstLength() const; static const ControllerExtension& getExtension(const tlm::tlm_generic_payload& trans); static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload& trans); @@ -264,7 +264,7 @@ private: public: //ChildExtension() = delete; - tlm::tlm_extension_base* clone() const override; + [[nodiscard]] tlm::tlm_extension_base* clone() const override; void copy_from(const tlm::tlm_extension_base& ext) override; tlm::tlm_generic_payload& getParentTrans(); static tlm::tlm_generic_payload& getParentTrans(tlm::tlm_generic_payload& childTrans); @@ -283,7 +283,7 @@ private: public: ParentExtension() = delete; - tlm_extension_base* clone() const override; + [[nodiscard]] tlm_extension_base* clone() const override; void copy_from(const tlm_extension_base& ext) override; static void setExtension(tlm::tlm_generic_payload& parentTrans, std::vector childTranses); const std::vector& getChildTranses(); @@ -294,7 +294,7 @@ public: class EccExtension : public tlm::tlm_extension { public: - tlm_extension_base* clone() const override + [[nodiscard]] tlm_extension_base* clone() const override { return new EccExtension; } diff --git a/src/libdramsys/DRAMSys/common/utils.h b/src/libdramsys/DRAMSys/common/utils.h index 47e3164e..1f3de24b 100644 --- a/src/libdramsys/DRAMSys/common/utils.h +++ b/src/libdramsys/DRAMSys/common/utils.h @@ -56,9 +56,9 @@ public: TimeInterval() : start(sc_core::SC_ZERO_TIME), end(sc_core::SC_ZERO_TIME) {} TimeInterval(const sc_core::sc_time& start, const sc_core::sc_time& end) : start(start), end(end) {} - sc_core::sc_time getLength() const; - bool timeIsInInterval(const sc_core::sc_time &time) const; - bool intersects(const TimeInterval &other) const; + [[nodiscard]] sc_core::sc_time getLength() const; + [[nodiscard]] bool timeIsInInterval(const sc_core::sc_time &time) const; + [[nodiscard]] bool intersects(const TimeInterval &other) const; }; constexpr const char headline[] = diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h index f3189285..83e7afca 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpec.h @@ -86,25 +86,25 @@ public: virtual ~MemSpec() = default; - virtual sc_core::sc_time getRefreshIntervalAB() const; - virtual sc_core::sc_time getRefreshIntervalPB() const; - virtual sc_core::sc_time getRefreshIntervalP2B() const; - virtual sc_core::sc_time getRefreshIntervalSB() const; + [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalAB() const; + [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalPB() const; + [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalP2B() const; + [[nodiscard]] virtual sc_core::sc_time getRefreshIntervalSB() const; - virtual unsigned getPer2BankOffset() const; + [[nodiscard]] virtual unsigned getPer2BankOffset() const; - virtual unsigned getRAAIMT() const; - virtual unsigned getRAAMMT() const; - virtual unsigned getRAADEC() const; + [[nodiscard]] virtual unsigned getRAAIMT() const; + [[nodiscard]] virtual unsigned getRAAMMT() const; + [[nodiscard]] virtual unsigned getRAADEC() const; - virtual bool hasRasAndCasBus() const; + [[nodiscard]] virtual bool hasRasAndCasBus() const; - virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0; - virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0; + [[nodiscard]] virtual sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload& payload) const = 0; + [[nodiscard]] virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload& payload) const = 0; - sc_core::sc_time getCommandLength(Command) const; - double getCommandLengthInCycles(Command) const; - uint64_t getSimMemSizeInBytes() const; + [[nodiscard]] sc_core::sc_time getCommandLength(Command) const; + [[nodiscard]] double getCommandLengthInCycles(Command) const; + [[nodiscard]] uint64_t getSimMemSizeInBytes() const; protected: MemSpec(const DRAMSys::Config::MemSpec& memSpec, diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h index a9db6433..f903de1d 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR3.h @@ -93,10 +93,10 @@ public: const double iDD3P0; const double iDD3P1; - sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h index 2849faca..1cf895d8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecDDR4.h @@ -100,10 +100,10 @@ public: const double iDD62; const double vDD2; - sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h index b9748814..7b1da4c2 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5.h @@ -90,11 +90,11 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h index 8c428d10..87ad3570 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR5X.h @@ -90,11 +90,11 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h index c45595d9..a216fca8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecGDDR6.h @@ -91,13 +91,13 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getRefreshIntervalP2B() const override; - unsigned getPer2BankOffset() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalP2B() const override; + [[nodiscard]] unsigned getPer2BankOffset() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; private: unsigned per2BankOffset; diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h index 2ccba274..b4c681c8 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecHBM2.h @@ -85,13 +85,13 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - bool hasRasAndCasBus() const override; + [[nodiscard]] bool hasRasAndCasBus() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h index 1daa2ab9..30db1f14 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecLPDDR4.h @@ -86,11 +86,11 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h index 7cb862ad..dd2e09d9 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecSTTMRAM.h @@ -78,8 +78,8 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h index d8e0042f..5f62b761 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO.h @@ -98,10 +98,10 @@ public: const double iDD62; const double vDD2; - sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h index 8547e640..3b418b62 100644 --- a/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h +++ b/src/libdramsys/DRAMSys/configuration/memspec/MemSpecWideIO2.h @@ -79,11 +79,11 @@ public: // Currents and Voltages: // TODO: to be completed - sc_core::sc_time getRefreshIntervalAB() const override; - sc_core::sc_time getRefreshIntervalPB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalAB() const override; + [[nodiscard]] sc_core::sc_time getRefreshIntervalPB() const override; - sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; - TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + [[nodiscard]] TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; }; } // namespace DRAMSys diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h index 6b29108a..357d95bc 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR3.h @@ -49,7 +49,7 @@ class CheckerDDR3 final : public CheckerIF { public: explicit CheckerDDR3(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h index c48aad81..c6762175 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerDDR4.h @@ -51,7 +51,7 @@ class CheckerDDR4 final : public CheckerIF { public: explicit CheckerDDR4(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h index 61067704..58de0e38 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5.h @@ -49,7 +49,7 @@ class CheckerGDDR5 final : public CheckerIF { public: explicit CheckerGDDR5(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h index 482f8e5e..50317f1c 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR5X.h @@ -49,7 +49,7 @@ class CheckerGDDR5X final : public CheckerIF { public: explicit CheckerGDDR5X(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h index c86de7f4..fbd4d385 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerGDDR6.h @@ -49,7 +49,7 @@ class CheckerGDDR6 final : public CheckerIF { public: explicit CheckerGDDR6(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h index 060e28f4..3da254e1 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerHBM2.h @@ -49,7 +49,7 @@ class CheckerHBM2 final : public CheckerIF { public: explicit CheckerHBM2(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h b/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h index df8bb8b1..35f0ecd4 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerIF.h @@ -47,7 +47,7 @@ class CheckerIF public: virtual ~CheckerIF() = default; - virtual sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const = 0; + [[nodiscard]] virtual sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const = 0; virtual void insert(Command command, const tlm::tlm_generic_payload& payload) = 0; }; diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h index 2cef3ddd..82203096 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerLPDDR4.h @@ -49,7 +49,7 @@ class CheckerLPDDR4 final : public CheckerIF { public: explicit CheckerLPDDR4(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h index 28d52e2e..f356ba28 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerSTTMRAM.h @@ -49,7 +49,7 @@ class CheckerSTTMRAM final : public CheckerIF { public: explicit CheckerSTTMRAM(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h index c39d1e41..f2f16146 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO.h @@ -49,7 +49,7 @@ class CheckerWideIO final : public CheckerIF { public: explicit CheckerWideIO(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: diff --git a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h index f68f551d..3fca11f7 100644 --- a/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h +++ b/src/libdramsys/DRAMSys/controller/checker/CheckerWideIO2.h @@ -49,7 +49,7 @@ class CheckerWideIO2 final : public CheckerIF { public: explicit CheckerWideIO2(const Configuration& config); - sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; + [[nodiscard]] sc_core::sc_time timeToSatisfyConstraints(Command command, const tlm::tlm_generic_payload& payload) const override; void insert(Command command, const tlm::tlm_generic_payload& payload) override; private: