Commit Graph

100 Commits

Author SHA1 Message Date
ed2a675145 Extract plausability check from AddressDecoder to separate function 2023-12-11 10:32:39 +01:00
74a9155993 Add RequestBufferSizeRead and RequestBufferSizeWrite configurations for ReadWrite Buffer 2023-11-14 11:00:28 +01:00
Lukas Steiner
8224e97abe Reformat all files. 2023-09-21 16:50:59 +02:00
a539e3c011 Merge branch 'develop' into work/partial_writes 2023-08-23 09:31:42 +02:00
a0f93a75e2 Merge develop 2023-08-21 10:01:08 +02:00
b30df49d67 Use tCCDMW for masked write in LPDDR4 2023-08-21 09:26:05 +02:00
c5f1320399 Implement Partial Write for DDR5 2023-08-16 09:38:57 +02:00
a4342f7104 Update expected traces for DDR5 and HBM3 2023-08-15 11:28:03 +02:00
a18bbc7465 Add the resource directory option to the json converter 2023-08-15 10:58:11 +02:00
c352ca4372 Remove compare.sh scripts and invoke sqldiff directly from CMake 2023-08-15 10:58:10 +02:00
b988544be2 Enable PerBank refresh in HBM2,HBM3 regression test 2023-08-15 10:58:10 +02:00
0fc74e93c4 Add LPDDR5 regression test 2023-08-15 10:58:10 +02:00
81eaccf3d6 Add lastCommandOn{C,R}asBus != scMaxTime check for HBM2 and HBM3 2023-08-15 10:58:10 +02:00
e3bd773cac Implement isFullCycle, alignAtNext functions in utils and add tests 2023-08-15 10:58:10 +02:00
599761c341 Add regression test for DDR5 2023-08-15 10:58:10 +02:00
42d1caa372 Add HBM3 regression test 2023-08-15 10:58:10 +02:00
14ecc64ed0 Introduce Simulator class 2023-07-14 14:31:03 +02:00
a9759f51fa Enable warnings in dev preset and fix them 2023-06-09 11:29:15 +02:00
Lukas Steiner
20f6aae787 Replace tabs with whitespaces. 2023-05-25 16:09:55 +02:00
Lukas Steiner
b3955d6d02 Update TUK to RPTU. 2023-05-25 15:15:52 +02:00
Lukas Steiner
93aecc3555 Merge branch 'gem5_instructions' into 'develop'
Add instructions for the new gem5 integration

See merge request ems/astdm/modeling.dram/dram.sys.5!23
2023-05-23 13:12:07 +00:00
Lukas Steiner
e389474139 Remove deprecated gem5 files. 2023-05-23 14:53:06 +02:00
69cd04c448 Namespace the complete DRAMSys library 2023-05-17 11:42:00 +02:00
e040e087a2 Fix sporadic CI/CD failures due to race condition
When running tests in parallel, there was a case where two tests
accessed the same generated resource. This is resolved by moving
all regression tests into their own subdirectory.
2023-04-26 15:25:05 +02:00
fa88b34052 Refactor deserilization of RefreshPolicyType and remove McConfig.cpp 2023-04-24 09:34:50 +02:00
85f944fe58 Rename RAACDR to RAADEC 2023-04-21 11:10:09 +02:00
aa07f071aa Update AddressDecoderTest 2023-04-13 11:34:27 +02:00
3d4f73361f Fix timings in new StlPlayer 2023-04-13 11:21:36 +02:00
a49afa40eb Use key "addressmapping" instead of "CONGEN" in addressmapping configs 2023-04-13 11:21:36 +02:00
b0d7e4a18b Add some cache test cases 2023-04-13 11:21:36 +02:00
a4fe32703c Set up testing infrastructure for Cache 2023-04-13 11:21:36 +02:00
45e31f5b5a First integration of Cache 2023-04-13 11:21:36 +02:00
c8e509a120 Add EccModule to simulator 2023-04-13 11:21:36 +02:00
2d0445d5a7 Introduce demonstrator for new simulator concept 2023-04-13 11:21:34 +02:00
d27a29ca80 Refactor configuration library
The configuration library has been refactored to make use of nlohmann
macros to reduce boilerplate code.
The nlohmann parser callback is used to decide whether to include
configuration json objects directly, or if they need to be loaded
from a sperate file.
2023-04-13 11:18:39 +02:00
c51e21ea69 Fix test_dramsys linker error 2023-03-22 12:57:25 +01:00
Lukas Steiner
e3b872446f Merge branch 'work/b_transport' into 'develop'
Implement b_transport and add tests

See merge request ems/astdm/modeling.dram/dram.sys.5!3
2023-03-22 09:51:17 +00:00
53d913c5f1 Make BlockingRead/WriteDelay configurable 2023-03-17 09:45:11 +01:00
bd899a2104 Integrate regression tests with CTest 2023-03-10 13:32:55 +01:00
aa0b8e9160 Use CMakePresets to define CI/CD configurations and introduce coverage target 2023-03-09 10:58:26 +01:00
ac9351c025 Implement b_transport and add tests for it 2023-03-06 14:10:56 +01:00
Lukas Steiner
823d473d97 Fix path in CI script. 2023-02-23 17:09:33 +01:00
Lukas Steiner
c4ca3d71d7 Reorganize config files, remove unused config. 2023-02-23 17:02:21 +01:00
Lukas Steiner
39b456d837 Use one stage for all tests. 2023-02-23 14:09:16 +01:00
Lukas Steiner
ac04ae66ce Retry CI needs with coverage. 2023-02-23 13:56:15 +01:00
Lukas Steiner
661819f381 Path fix for DDR3 test. 2023-02-23 11:36:17 +01:00
Lukas Steiner
d736a2d25e Fix regression tests, add DRAMPower. 2023-02-23 10:38:59 +01:00
Thomas Psota
f434026ccd Added extension mechanism and ported DDR5, LPDDR5, HBM3, TraceAnalyzer 2023-02-09 14:22:34 +01:00
Lukas Steiner
9760ffe5cc Add regression test files. 2023-01-30 15:45:10 +01:00
Thomas Psota
b63c9beb50 Intensive refactor of DRAMSys project structure and CMakeFiles 2022-12-14 15:51:46 +01:00