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606d273bee60c0e9cd4ac4c415e32c763d8d44bf
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Author SHA1 Message Date
Lukas Steiner (2)
606d273bee Included memspec and dram component for HBM2. 2019-10-10 15:21:58 +02:00
Lukas Steiner (2)
256abe449c Included CheckerWideIO2, tPPD fix in CheckerLPDDR4. 2019-10-09 09:49:46 +02:00
Lukas Steiner (2)
a5b00ea3be Further inclusion of WideIO2. 2019-10-08 15:27:18 +02:00
Lukas Steiner (2)
65db413a20 Included MemSpecWideIO2, some adaptions for all memspecs. 2019-10-08 14:14:42 +02:00
Lukas Steiner (2)
932027112e Adapted timing checkers of DDR4 and WideIO to new refresh. 2019-10-07 15:37:23 +02:00
Lukas Steiner
86d5082434 Further improvements in refresh managers. 2019-10-06 20:54:30 +02:00
Lukas Steiner
d1f6bc6233 Improved flexible refresh, implemented first version of bankwise flexible refresh. 2019-10-06 18:56:13 +02:00
Lukas Steiner
aa6a205872 Implemented first version of flexible refresh (only REFA). 2019-10-04 21:46:29 +02:00
Lukas Steiner
b22cfa4a94 Improved controller method, some code and output formatting. 2019-10-03 19:04:34 +02:00
Lukas Steiner
6e71e435c5 Implemented first version of new bankwise refresh. 2019-10-02 21:55:19 +02:00
Lukas Steiner
4328f4550b Updated CheckerLPDDR4 for new refresh, some renaming. 2019-10-02 21:54:05 +02:00
Lukas Steiner
f4a018cfb3 Fixed display of rankwise commands. 2019-10-02 17:46:37 +02:00
Lukas Steiner
abb9a37096 Added numberOfRanks to database. 2019-10-02 16:08:10 +02:00
Lukas Steiner
7868af4b51 Implemented first version of new refresh (no REFB). 2019-10-01 20:53:01 +02:00
Lukas Steiner
04ec683b57 Included LPDDR4 timing checker and example. 2019-09-26 21:31:17 +02:00
Lukas Steiner
4950a2587e Included LPDDR4 memspec and Dram, changed structure of MemSpec.h, removed ScheduledCommand. 2019-09-26 16:55:20 +02:00
Lukas Steiner
8b7760a585 LPDDR4 address mapping and memspec. 2019-09-26 16:49:40 +02:00
Lukas Steiner (2)
47949922f3 Included LPDDR4 memspec. 2019-09-26 13:26:17 +02:00
Lukas Steiner (2)
cfbce483bd Included timing checker for DDR4. 2019-09-24 15:18:37 +02:00
Lukas Steiner (2)
2690755024 Included JEDEC based memspecs, address mapping and simulation for DDR4. 2019-09-24 15:17:25 +02:00
Lukas Steiner (2)
149bfee201 Corrected refresh mode (1x, 2x and 4x) for DDR4. 2019-09-24 15:16:09 +02:00
Lukas Steiner (2)
805490d05c Correction of address mappings. 2019-09-24 14:14:56 +02:00
Lukas Steiner
fc10f72773 Minor changes in address mapping and configuration. 2019-09-23 22:16:56 +02:00
Lukas Steiner (2)
102b0667fd Added bankgroups to address decoding. 2019-09-23 20:07:00 +02:00
Lukas Steiner (2)
bda10dca2f Individual memspec files for different DRAMs. 2019-09-23 14:31:47 +02:00
Lukas Steiner (2)
c1b741d89b Changed directory of configuration, added attribute unused to suppress warnings. 2019-09-23 13:24:47 +02:00
Lukas Steiner (2)
650e1d405b Removed ScheduledCommand dependencies. 2019-09-23 10:23:02 +02:00
Lukas Steiner
5fe5529c7c Included various command lengths. 2019-09-20 17:35:01 +02:00
Lukas Steiner
97542d5f97 Included missing memory allocation in Dram. 2019-09-19 14:46:55 +02:00
Lukas Steiner
d06d9eec2c Changed data structures of timing checkers from ScheduledCommand to sc_time. 2019-09-19 14:45:38 +02:00
Lukas Steiner
b918f0f9ea Added ranks to tdb files and TraceAnalyzer. 2019-09-18 18:24:10 +02:00
Lukas Steiner
330b07d0e7 Changed data structures of Address Decoder for speedup. 2019-09-18 16:39:38 +02:00
Lukas Steiner
6eef8ff1e6 Rank inclusion part 2. 2019-09-17 21:31:57 +02:00
Lukas Steiner
5d7495383e Changed internal data structures from std::map to std::vector for faster access. 2019-09-17 18:16:52 +02:00
Lukas Steiner (2)
3a7557544f Rank inclusion part 1. 2019-09-16 15:16:14 +02:00
Lukas Steiner (2)
b9700f1ee5 Implemented some basics for ranks. 2019-09-12 14:56:06 +02:00
Lukas Steiner (2)
26c3bd23c1 Changed default colour grouping to phase. 2019-09-12 10:55:59 +02:00
Lukas Steiner
fcde31f041 Included adaptive page policy. 2019-09-11 20:36:45 +02:00
Lukas Steiner (2)
62841a3590 Implemented closed page policy. Fixed bug in trace analyzer tests. 2019-09-11 16:02:36 +02:00
Lukas Steiner (2)
7fd5f05d3e Renaming of ControllerNew to Controller. 2019-09-11 09:59:51 +02:00
Lukas Steiner (2)
7827a5f869 Added some addressmappings and memspecs for WIDEIO and WIDEIO2. 2019-09-10 15:22:05 +02:00
Lukas Steiner (2)
f40ace826b Changed DRAMPower submodule commit and branch. 2019-08-26 17:14:23 +02:00
Lukas Steiner (2)
7934d2e160 Renaming libDRAMPowerIF to libDRAMPowerDummy. 2019-08-26 16:26:28 +02:00
Lukas Steiner
2402180a9c Merge branch 'DRAMSys4.0_ctrl' of https://git.eit.uni-kl.de/ems/astdm/dram.sys into DRAMSys4.0_ctrl 2019-08-25 23:14:19 +02:00
Lukas Steiner
d4943bccc5 Debug Manager cleanup. 2019-08-25 23:13:05 +02:00
Lukas Steiner (2)
98c52b8a3e Merge remote-tracking branch 'origin/master' into DRAMSys4.0_ctrl 
# Conflicts:
#	DRAMSys/library/src/simulation/MemoryManager.cpp
 2019-08-23 09:54:56 +02:00
Matthias Jung
f6072e9d4f Fixed Memory Leak 
As pointed out by @sprado, there was a memory leak in the STL player.
The data pointer was allocated, but never deleted again. Some lines for
deletion were commented out in the memory manager in the free function.
These two lines regarding the deletion of data were moved into the
destructor of the memory manager. The allocation of the data is done in
the allocate() function of the memory manager when a new payload is
generated.
 2019-08-22 23:11:48 +02:00
Matthias Jung
d55d801a04 Merge branch 'master' of https://git.eit.uni-kl.de/ems/astdm/dram.sys 2019-08-22 23:03:05 +02:00
Matthias Jung
a6f679b86b Add compile flag for macOS 2019-08-22 23:00:38 +02:00
Matthias Jung
9702d7a8f3 Add compile flag for macOS 2019-08-22 22:59:23 +02:00