25c729de1d
Replace deprecated option in .clang-format
2023-08-29 09:24:20 +02:00
77ee1b2017
Remove .astylerc as .clang-format is now used
2023-08-29 09:22:45 +02:00
1bb3c3ea0f
Use raw string literal for database creation
2023-08-29 09:22:45 +02:00
Lukas Steiner
8695efb2f9
Merge branch 'work/partial_writes' into 'develop'
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First implementation of Partial Writes
See merge request ems/astdm/modeling.dram/dram.sys.5!41
2023-08-23 13:35:55 +00:00
Lukas Steiner
ccb4ee592b
Remove masked write from GDDR checkers.
2023-08-23 15:30:15 +02:00
Lukas Steiner
12f2b73cde
Additional check of byte enable pointer.
2023-08-23 15:21:53 +02:00
Lukas Steiner
76e58b1755
Fix renaming.
2023-08-23 13:50:10 +02:00
Lukas Steiner
0f824e8b92
Do not allow masked write in default case.
2023-08-23 11:41:58 +02:00
Lukas Steiner
8c248e8e23
Remove masked write checks for HBM3.
2023-08-23 10:40:41 +02:00
a539e3c011
Merge branch 'develop' into work/partial_writes
2023-08-23 09:31:42 +02:00
0d67a1fc2b
Support byte_enable_ptr for debug transport
2023-08-22 11:26:28 +02:00
47bdddc5f1
Different tCCDMW timing when previous WR had BL32 in LPDDR4
2023-08-22 09:41:36 +02:00
Lukas Steiner
5250adea3c
Merge branch 'clang-tidy-refactor' into 'develop'
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Use clang-tidy and clang-format tooling
See merge request ems/astdm/modeling.dram/dram.sys.5!20
2023-08-21 11:53:12 +00:00
4548d20b6e
Rename requiresMaskedWrite to requiresReadModifyWrite
2023-08-21 10:55:41 +02:00
c0f1b2f6a3
Add check to prevent masked writes in HBM3
2023-08-21 10:52:44 +02:00
f1cfb80337
Minor readability fixes
2023-08-21 10:10:49 +02:00
a0f93a75e2
Merge develop
2023-08-21 10:01:08 +02:00
b30df49d67
Use tCCDMW for masked write in LPDDR4
2023-08-21 09:26:05 +02:00
b3937cf63a
Add LPDDR5 Partial Write Support
2023-08-16 11:42:39 +02:00
3f0372f1f7
Add Partial Write support for blocking accesses
2023-08-16 09:45:32 +02:00
09275bb789
Add support for MWR and MWRA to TraceAnalyzer
2023-08-16 09:38:57 +02:00
570fb985df
Fix MWR and MWRA command lengths for LPDDR4
2023-08-16 09:38:57 +02:00
c5f1320399
Implement Partial Write for DDR5
2023-08-16 09:38:57 +02:00
40dbc518b6
Add hack in TimingCheckers to convert MWR to WR in insertion stage
2023-08-16 09:38:54 +02:00
f7066a22b0
First implementation of Partial Writes
2023-08-16 09:38:54 +02:00
Lukas Steiner
a8d15e35a5
Merge branch 'work/regression_tests' into 'develop'
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Add a regression test for every standard
See merge request ems/astdm/modeling.dram/dram.sys.5!34
2023-08-15 12:00:48 +00:00
Lukas Steiner
5598d53ebd
Merge branch 'cmake_debug' into 'develop'
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Disable CMake diagnostics print
See merge request ems/astdm/modeling.dram/dram.sys.5!40
2023-08-15 09:28:28 +00:00
a4342f7104
Update expected traces for DDR5 and HBM3
2023-08-15 11:28:03 +02:00
a18bbc7465
Add the resource directory option to the json converter
2023-08-15 10:58:11 +02:00
c352ca4372
Remove compare.sh scripts and invoke sqldiff directly from CMake
2023-08-15 10:58:10 +02:00
b988544be2
Enable PerBank refresh in HBM2,HBM3 regression test
2023-08-15 10:58:10 +02:00
0fc74e93c4
Add LPDDR5 regression test
2023-08-15 10:58:10 +02:00
81eaccf3d6
Add lastCommandOn{C,R}asBus != scMaxTime check for HBM2 and HBM3
2023-08-15 10:58:10 +02:00
e3bd773cac
Implement isFullCycle, alignAtNext functions in utils and add tests
2023-08-15 10:58:10 +02:00
599761c341
Add regression test for DDR5
2023-08-15 10:58:10 +02:00
42d1caa372
Add HBM3 regression test
2023-08-15 10:58:10 +02:00
Lukas Steiner
56c9f5f5f0
Merge branch 'initialize_generalinfotable' into 'develop'
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Write GeneralInfo table at the beginning
See merge request ems/astdm/modeling.dram/dram.sys.5!39
2023-08-14 13:33:40 +00:00
Lukas Steiner
962cc5cf30
Merge branch 'bugfix_includes' into 'develop'
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Fix includes that cause build errors on some platforms
See merge request ems/astdm/modeling.dram/dram.sys.5!38
2023-08-14 11:36:57 +00:00
Lukas Steiner
766e12fff1
Merge branch 'bugfix/initiator' into 'develop'
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Fix a timing issue in the traffic initiator
See merge request ems/astdm/modeling.dram/dram.sys.5!37
2023-08-14 09:14:50 +00:00
Lukas Steiner
b5fb23b55d
Merge branch 'debug_file' into 'develop'
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Don't create log file when debug is not enabled
See merge request ems/astdm/modeling.dram/dram.sys.5!36
2023-08-10 12:27:54 +00:00
Lukas Steiner
cb9689a08d
Merge branch 'work/simulator_library' into 'develop'
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Introduce Simulator class
See merge request ems/astdm/modeling.dram/dram.sys.5!35
2023-08-10 12:19:33 +00:00
Lukas Steiner
dc8c564c97
Merge branch 'feat/type_safe_index_vector' into 'develop'
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Use type safe index vectors in controller.
See merge request ems/astdm/modeling.dram/dram.sys.5!32
2023-08-10 11:43:35 +00:00
a6e1f83570
Remove unnecessary includes from Cache
2023-08-09 16:00:43 +02:00
ccc1bc73c4
Disable CMake diagnostics print
2023-08-09 14:57:29 +02:00
d392d0ab98
Write GeneralInfo table at the beginning
...
and do not include information in it that is only known at the end of
the simulation. These can trivially be calculated by the trace itself
and would be redundant information regardless.
The TraceAnalyzer gets the number of transactions and the length of
the trace by additional SQL queries.
This enables us to inspect traces of simulations that were aborted
without finishing cleanlywithout finishing cleanly.
2023-08-09 11:55:10 +02:00
a064f46413
Fix includes that cause build errors on some platforms
2023-08-03 15:04:39 +02:00
24654be952
Fix a timing issue in the traffic initiator
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When the generator clock did not match the memory clock,
the generator always created a constant delay to the
next transaction.
This is not correct as due to rounding, the delay should be
one cycle more or less depending on the current simulation time.
2023-07-27 11:02:45 +02:00
085bfbd8de
Don't create log file when debug is not enabled
2023-07-21 09:39:52 +02:00
14ecc64ed0
Introduce Simulator class
2023-07-14 14:31:03 +02:00
Lukas Steiner
cacbf59d96
Missing refactoring.
2023-06-30 16:04:23 +02:00
