e040e087a2
Fix sporadic CI/CD failures due to race condition
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When running tests in parallel, there was a case where two tests
accessed the same generated resource. This is resolved by moving
all regression tests into their own subdirectory.
2023-04-26 15:25:05 +02:00
Lukas Steiner
58d486fb82
Merge branch 'work/hbm_rfm_fixes' into 'develop'
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HBM and RFM fixes
See merge request ems/astdm/modeling.dram/dram.sys.5!17
2023-04-26 08:36:08 +00:00
fa88b34052
Refactor deserilization of RefreshPolicyType and remove McConfig.cpp
2023-04-24 09:34:50 +02:00
156c558e32
Resize sample HBM3 memspec and address mapping to 8 Gib
2023-04-21 11:14:41 +02:00
44a4d71635
Fix HBM pseudochannels not respeced in AddressDecoder
2023-04-21 11:12:21 +02:00
85f944fe58
Rename RAACDR to RAADEC
2023-04-21 11:10:09 +02:00
Lukas Steiner
7c0198cf21
Change default simulation file back to DDR4.
2023-04-20 10:38:33 +02:00
Lukas Steiner
515962e7ae
Merge branch 'simconfig_fix' into 'develop'
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Fix DatabaseRecording and SimulationProgressBar fields in SimConfig
See merge request ems/astdm/modeling.dram/dram.sys.5!15
2023-04-14 12:10:58 +00:00
0814aa0cf1
Fix DatabaseRecording and SimulationProgressBar fields in SimConfig
2023-04-14 14:04:31 +02:00
Lukas Steiner
0a8badf2ae
Merge branch 'wip/unit_test_preps' into 'develop'
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Move timing checks out of controller managers (BM, RM, PDM).
See merge request ems/astdm/modeling.dram/dram.sys.5!14
2023-04-14 11:33:14 +00:00
Lukas Steiner
9a1443835d
Merge branch 'develop' into wip/unit_test_preps
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# Conflicts:
# extensions/standards/DDR5/DRAMSys/controller/checker/CheckerDDR5.cpp
2023-04-14 11:35:32 +02:00
Lukas Steiner
b1372647cf
Merge branch 'work/demonstrator' into 'develop'
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New DRAMSys simulator approach
See merge request ems/astdm/modeling.dram/dram.sys.5!5
2023-04-14 09:28:01 +00:00
Lukas Steiner
f844449d50
Remove empty cpp files.
2023-04-14 11:21:36 +02:00
ad4277c0ee
Enable DatabaseRecording by default again
2023-04-14 11:11:40 +02:00
Lukas Steiner
9b31fef555
Use local copies of sc_max_time() instead of calling the function.
2023-04-14 10:03:59 +02:00
Lukas Steiner
9115845862
Add common interface for BM, RM and PDM (2).
2023-04-13 16:10:59 +02:00
Lukas Steiner
7c33d48398
Add common interface for BM, RM and PDM.
2023-04-13 16:09:00 +02:00
aa07f071aa
Update AddressDecoderTest
2023-04-13 11:34:27 +02:00
b343ea821f
Refactor Configuration and add warnings when invalid values are provided
2023-04-13 11:21:37 +02:00
8f6e55f9fa
Enable StoreMode in new simulator and some refactoring
2023-04-13 11:21:36 +02:00
1f161b412f
Update documentation
2023-04-13 11:21:36 +02:00
56d43ac1d4
Remove dead function in RequestIssuer
2023-04-13 11:21:36 +02:00
3cd6396207
Add "dataAlignment" field for random traffic generators
2023-04-13 11:21:36 +02:00
15075c3be0
Use predefined resource directory if none is specified
2023-04-13 11:21:36 +02:00
fb174392bb
Only use DRAMSysRecorable when recording is enabled
2023-04-13 11:21:36 +02:00
0914d736e4
Fix resource directory path in new simulator
2023-04-13 11:21:36 +02:00
03152c0e61
Fix dump of mcconfig and memspec in GeneralInfo table
2023-04-13 11:21:36 +02:00
3d4f73361f
Fix timings in new StlPlayer
2023-04-13 11:21:36 +02:00
a49afa40eb
Use key "addressmapping" instead of "CONGEN" in addressmapping configs
2023-04-13 11:21:36 +02:00
b0d7e4a18b
Add some cache test cases
2023-04-13 11:21:36 +02:00
a4fe32703c
Set up testing infrastructure for Cache
2023-04-13 11:21:36 +02:00
45e31f5b5a
First integration of Cache
2023-04-13 11:21:36 +02:00
c8e509a120
Add EccModule to simulator
2023-04-13 11:21:36 +02:00
2d0445d5a7
Introduce demonstrator for new simulator concept
2023-04-13 11:21:34 +02:00
d27a29ca80
Refactor configuration library
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The configuration library has been refactored to make use of nlohmann
macros to reduce boilerplate code.
The nlohmann parser callback is used to decide whether to include
configuration json objects directly, or if they need to be loaded
from a sperate file.
2023-04-13 11:18:39 +02:00
Lukas Steiner
0d09222ab5
Implement cache into checker.
2023-04-13 11:07:55 +02:00
Lukas Steiner
65a20e9827
Remove checker from BM, RM and PDM.
2023-04-13 09:57:50 +02:00
Lukas Steiner
088621880c
Rename methods to evaluate and update.
2023-04-12 16:47:26 +02:00
Lukas Steiner
a95db95030
Merge branch 'work/DDR5' into 'develop'
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Implement new DDR5 tCCD_M timings
See merge request ems/astdm/modeling.dram/dram.sys.5!13
2023-04-12 13:53:39 +00:00
Lukas Steiner
5f1c74790b
Remove duplicate checks in DDR5 checker.
2023-04-12 13:45:44 +00:00
507c1d32d6
Update tCCD_L_WR, tCCD_L_WR2 and tCCD_M_WR timings in DDR5 timing checker
2023-04-12 09:40:18 +02:00
949cf944bc
Update tCCD_M timings in memspecs for DDR5
2023-04-11 14:27:26 +02:00
60b2bcbffa
Fix DDR5 write-to-write delay in TimingChecker
2023-04-11 14:08:32 +02:00
49954df6ee
Add tCCD_M DDR5 timings, MemSpecs still incomplete
2023-04-06 10:38:48 +02:00
Lukas Steiner
daecc19252
Merge branch 'lpddr5' into 'develop'
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Add LPDDR5X configurations and separate tRCD into tRCDRD and tRCDWR
See merge request ems/astdm/modeling.dram/dram.sys.5!12
2023-03-30 13:12:30 +00:00
Lukas Steiner
b086fa985d
Change names of LPDDR5 timings from tRCDRD/tRCDWR to tRCD_L/tRCD_S.
2023-03-30 15:06:17 +02:00
5d7171e537
Add LPDDR5X configurations and separate tRCD into tRCDRD and tRCDWR
2023-03-29 16:49:15 +02:00
Lukas Steiner
b29c67481d
Merge branch 'fix/plots' into 'develop'
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Update plots python script to new database layout
See merge request ems/astdm/modeling.dram/dram.sys.5!11
2023-03-24 13:24:49 +00:00
Lukas Steiner
964e4949cc
Merge branch 'bug/payload_id_github' into 'develop'
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Increment nextChannelPayloadIDToAppend only once.
See merge request ems/astdm/modeling.dram/dram.sys.5!10
2023-03-24 08:50:04 +00:00
6cb2128612
Update plots python script to new database layout
2023-03-24 09:18:06 +01:00
