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d94ef08a365e51cc5fc341d76f7114d78c663caa
gem5/src/arch/riscv
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Roger Chang d94ef08a36 arch-riscv: Fix fence.i instruction in O3 CPU 
We should clean the instruction buffer after the fence.i is execute
to avoid execute old instruction for self-modifying code

Change-Id: Iece0ee0d10631fcd9bd17ee67cf0c92f72acdbd8
2024-01-29 11:43:27 +08:00
..
bare_metal
arch-riscv: Insert symbol table of bootloader into debug symbol table
2023-04-13 00:10:47 +00:00
gdb-xml
arch-riscv: Support RV32 to remote gdb
2022-12-13 05:21:27 +00:00
insts
arch-riscv: Fix narrow datatypes in RVV isa files (#606)
2023-11-29 10:11:06 -08:00
isa
arch-riscv: Fix fence.i instruction in O3 CPU
2024-01-29 11:43:27 +08:00
linux
arch-riscv: Add PCEvent for RISCV FS Workload kernel panic/oops
2023-12-04 14:59:26 -08:00
regs
arch-riscv: Add isaExts field for CSR registers
2023-11-28 09:26:27 +08:00
decoder.cc
arch-riscv: Add elen configuration to vector config instructions
2023-10-19 00:27:58 +02:00
decoder.hh
arch-riscv: Add elen configuration to vector config instructions
2023-10-19 00:27:58 +02:00
faults.cc
arch-riscv: Handle the exception following the privilege mode set
2023-11-28 09:26:27 +08:00
faults.hh
arch-riscv: Add risc-v vector regs and configs
2023-08-02 14:46:35 +02:00
fp_inst.hh
arch-riscv: When an inst generates a fault, return it immediately.
2021-05-20 23:42:13 +00:00
idle_event.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
idle_event.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
interrupts.hh
arch-riscv: Handle the exception following the privilege mode set
2023-11-28 09:26:27 +08:00
isa.cc
arch-riscv: Handle the exception following the privilege mode set
2023-11-28 09:26:27 +08:00
isa.hh
arch-riscv: define the CSR masks for each privilege modes
2023-11-28 09:26:27 +08:00
Kconfig
scons: Use Kconfig to configure gem5.
2023-11-23 08:26:10 +08:00
mmu.hh
arch: Make the MMU ranged translateFunction pure virtual.
2021-10-22 21:43:02 +00:00
page_size.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable_walker.cc
arch-riscv: squash walks with tlb hits in startWalkWrapper
2023-12-13 16:40:46 +01:00
pagetable_walker.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
pagetable.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pcstate.hh
arch-riscv: Initial the privilege modes configuration
2023-11-28 09:26:27 +08:00
pma_checker.cc
arch-riscv: Move PMAChecker and PMP to RiscvISA namespace (#691)
2024-01-10 16:58:13 -08:00
pma_checker.hh
arch-riscv: Move PMAChecker and PMP to RiscvISA namespace (#691)
2024-01-10 16:58:13 -08:00
PMAChecker.py
arch-riscv: Move PMAChecker and PMP to RiscvISA namespace (#691)
2024-01-10 16:58:13 -08:00
pmp.cc
arch-riscv: Move PMAChecker and PMP to RiscvISA namespace (#691)
2024-01-10 16:58:13 -08:00
pmp.hh
arch-riscv: Move PMAChecker and PMP to RiscvISA namespace (#691)
2024-01-10 16:58:13 -08:00
PMP.py
arch-riscv: Move PMAChecker and PMP to RiscvISA namespace (#691)
2024-01-10 16:58:13 -08:00
pra_constants.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
process.cc
arch-riscv: fatal_if the process run without SU modes
2023-11-28 09:26:27 +08:00
process.hh
base: Remove the Loader namespace
2023-01-17 09:16:20 +00:00
reg_abi.cc
arch-riscv,sim-se: Support RV32 register ABI call
2023-02-02 04:50:04 +00:00
reg_abi.hh
arch-riscv,sim-se: Support RV32 register ABI call
2023-02-02 04:50:04 +00:00
remote_gdb.cc
arch-riscv: Add misa rvs check for memory translation
2023-11-28 09:26:27 +08:00
remote_gdb.hh
arch,base,dev,sim: Convert objects to use the HostSocket param type.
2023-04-12 02:18:22 +00:00
RiscvCPU.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
RiscvDecoder.py
arch-riscv: Add fatal if RVV used with o3 or minor
2023-08-02 14:46:36 +02:00
RiscvFsWorkload.py
arch-riscv: Add PCEvent for RISCV FS Workload kernel panic/oops
2023-12-04 14:59:26 -08:00
RiscvInterrupts.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
RiscvISA.py
misc,python: Add isort hook to pre-commit (#431)
2023-11-30 09:54:12 +00:00
RiscvMMU.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
RiscvSeWorkload.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
RiscvTLB.py
misc: Run pre-commit run --all-files
2023-11-29 22:06:41 -08:00
rvk.hh
arch-riscv: Add RV32 only Zk instruction extensions
2023-05-03 00:42:37 +00:00
SConscript
arch-riscv: Initial the privilege modes configuration
2023-11-28 09:26:27 +08:00
se_workload.hh
arch-riscv,sim-se: Support RV32 register ABI call
2023-02-02 04:50:04 +00:00
stacktrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
tlb.cc
arch-riscv: Remove the check of bit 63 of the physical address (#756)
2024-01-12 15:17:49 -08:00
tlb.hh
arch-riscv: squash walks with tlb hits in startWalkWrapper
2023-12-13 16:40:46 +01:00
types.hh
arch-riscv: Add vlen configuration to vector instructions
2023-10-19 00:27:58 +02:00
utility.hh
arch-riscv: Refactor the RISC-V multiplication utility (#780)
2024-01-18 12:40:11 -08:00