Files
gem5/src/arch/riscv/RiscvDecoder.py
Jason Lowe-Power af1b2ec2d5 arch-riscv: Add fatal if RVV used with o3 or minor
Since the O3 and Minor CPU models do not support RVV right now as the
implementation stalls the decode until vsetvl instructions are exectued,
this change calls `fatal` if RVV is not explicitly enabled.

It is possible to override this if you explicitly enable RVV in the
config file.

Change-Id: Ia801911141bb2fb2bedcff3e139bf41ba8936085
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2023-08-02 14:46:36 +02:00

34 lines
1.7 KiB
Python

# Copyright 2021 Google, Inc.
#
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from m5.objects.InstDecoder import InstDecoder
from m5.params import *
class RiscvDecoder(InstDecoder):
type = "RiscvDecoder"
cxx_class = "gem5::RiscvISA::Decoder"
cxx_header = "arch/riscv/decoder.hh"