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arch-riscv: Add misa rvs check for memory translation

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The memory translation require supervisor mode implement. If the
supervisor mode is not implemented, the satp CSR is not exists and
should not do address translation

Change-Id: Ie6c8a1a130d0aab0647b35e0f731f6b930834176
This commit is contained in:
Roger Chang
2023-10-31 15:26:37 +08:00
parent 6fd4feb797
commit d56801c240
2 changed files with 8 additions and 3 deletions
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3
src/arch/riscv/remote_gdb.cc
View File

@@ -218,7 +218,8 @@ RemoteGDB::acc(Addr va, size_t len)
PrivilegeMode pmode = mmu->getMemPriv(context(), BaseMMU::Read);
SATP satp = context()->readMiscReg(MISCREG_SATP);
if (pmode != PrivilegeMode::PRV_M &&
MISA misa = tc->readMiscRegNoEffect(MISCREG_ISA);
if (misa.rvs && pmode != PrivilegeMode::PRV_M &&
satp.mode != AddrXlateMode::BARE) {
Walker *walker = mmu->getDataWalker();
Fault fault = walker->startFunctional(

8
src/arch/riscv/tlb.cc
View File

@@ -341,9 +341,12 @@ TLB::translate(const RequestPtr &req, ThreadContext *tc,
if (FullSystem) {
PrivilegeMode pmode = getMemPriv(tc, mode);
MISA misa = tc->readMiscRegNoEffect(MISCREG_ISA);
SATP satp = tc->readMiscReg(MISCREG_SATP);
if (pmode == PrivilegeMode::PRV_M || satp.mode == AddrXlateMode::BARE)
if (!misa.rvs || pmode == PrivilegeMode::PRV_M ||
satp.mode == AddrXlateMode::BARE) {
req->setFlags(Request::PHYSICAL);
}
Fault fault;
if (req->getFlags() & Request::PHYSICAL) {
@@ -434,8 +437,9 @@ TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc,
MMU *mmu = static_cast<MMU *>(tc->getMMUPtr());
PrivilegeMode pmode = mmu->getMemPriv(tc, mode);
MISA misa = tc->readMiscRegNoEffect(MISCREG_ISA);
SATP satp = tc->readMiscReg(MISCREG_SATP);
if (pmode != PrivilegeMode::PRV_M &&
if (misa.rvs && pmode != PrivilegeMode::PRV_M &&
satp.mode != AddrXlateMode::BARE) {
Walker *walker = mmu->getDataWalker();
unsigned logBytes;