Roger Chang d94ef08a36 arch-riscv: Fix fence.i instruction in O3 CPU ...

We should clean the instruction buffer after the fence.i is execute
to avoid execute old instruction for self-modifying code

Change-Id: Iece0ee0d10631fcd9bd17ee67cf0c92f72acdbd8

2024-01-29 11:43:27 +08:00

..

formats

arch-riscv: Add isaExts field for CSR registers

2023-11-28 09:26:27 +08:00

templates

arch-riscv: Fix issue when vl=0 in VectorIntMaskMacroConstructor (#715)

2024-01-17 08:45:08 -08:00

bitfields.isa

arch-riscv: Implement Zcb instructions

2023-10-05 18:46:35 +08:00

decoder.isa

arch-riscv: Fix fence.i instruction in O3 CPU

2024-01-29 11:43:27 +08:00

includes.isa

arch-riscv: Move VMem implementation from header to source

2023-10-26 18:04:58 +08:00

main.isa

arch-riscv: Add risc-v vector ext v1.0 mem insts support

2023-08-02 14:46:35 +02:00

operands.isa

arch-riscv: Change the implementation of vset*vl*

2023-09-12 13:56:21 +08:00