arch-riscv: Change the implementation of vset*vl*

The changes includes:

1. Add VL, Vtype and VlenbBits operands
2. Change R/W methods of VL, Vtype and VlenbBits from PCState

Change-Id: I0531ddc14344f2cca94d0e750a3b4291e0227d54

src/arch/riscv/decoder.cc

@@ -101,9 +101,7 @@ Decoder::moreBytes(const PCStateBase &pc, Addr fetchPC)
         }
     }
     if (instDone) {
-        emi.vl      = this->machVl;
-        emi.vtype8   = this->machVtype & 0xff;
-        emi.vill    = this->machVtype.vill;
+
         if (vconf(emi)) {
             this->vConfigDone = false; // set true when vconfig inst execute
         }
@@ -142,6 +140,9 @@ Decoder::decode(PCStateBase &_next_pc)
         next_pc.compressed(false);
     }
 
+    emi.vl      = next_pc.vl();
+    emi.vtype8  = next_pc.vtype() & 0xff;
+    emi.vill    = next_pc.vtype().vill;
     emi.rv_type = static_cast<int>(next_pc.rvType());
     return decode(emi, next_pc.instAddr());
 }

src/arch/riscv/isa/decoder.isa

@@ -4359,8 +4359,13 @@ decode QUADRANT default Unknown::unknown() {
                         uint64_t rs1_bits = RS1;
                         uint64_t requested_vl = Rs1_ud;
                         uint64_t requested_vtype = zimm11;
-
-                        Rd_ud = 0;
+                        uint32_t vlen = VlenbBits * 8;
+                        uint32_t vlmax = getVlmax(Vtype, vlen);
+                        uint32_t current_vl = VL;
+                    }}, {{
+                        Rd_ud = new_vl;
+                        VL = new_vl;
+                        Vtype = new_vtype;
                     }}, VectorConfigOp, IsSerializeAfter, IsNonSpeculative);
                     0x1: decode BIT30 {
                         0x0: vsetvl({{
@@ -4368,8 +4373,13 @@ decode QUADRANT default Unknown::unknown() {
                             uint64_t rs1_bits = RS1;
                             uint64_t requested_vl = Rs1_ud;
                             uint64_t requested_vtype = Rs2_ud;
-
-                            Rd_ud = 0;
+                            uint32_t vlen = VlenbBits * 8;
+                            uint32_t vlmax = getVlmax(Vtype, vlen);
+                            uint32_t current_vl = VL;
+                        }}, {{
+                            Rd_ud = new_vl;
+                            VL = new_vl;
+                            Vtype = new_vtype;
                         }}, VectorConfigOp, IsSerializeAfter,
                         IsNonSpeculative);
                         0x1: vsetivli({{
@@ -4377,8 +4387,13 @@ decode QUADRANT default Unknown::unknown() {
                             uint64_t rs1_bits = -1;
                             uint64_t requested_vl = uimm;
                             uint64_t requested_vtype = zimm10;
-
-                            Rd_ud = 0;
+                            uint32_t vlen = VlenbBits * 8;
+                            uint32_t vlmax = getVlmax(Vtype, vlen);
+                            uint32_t current_vl = VL;
+                        }}, {{
+                            Rd_ud = new_vl;
+                            VL = new_vl;
+                            Vtype = new_vtype;
                         }}, VectorConfigOp, IsSerializeAfter,
                         IsNonSpeculative);
                     }

src/arch/riscv/isa/formats/vector_conf.isa

@@ -27,8 +27,17 @@
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 
-def format VConfOp(code, *flags) {{
-    iop = InstObjParams(name, Name, 'VConfOp', code, flags)
+def format VConfOp(code, write_code, *flags) {{
+    iop = InstObjParams(
+        name,
+        Name,
+        'VConfOp',
+        {
+            'code': code,
+            'write_code': write_code,
+        },
+        flags
+    )
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
@@ -54,11 +63,8 @@ def template VConfExecute {{
 
         tc->setMiscReg(MISCREG_VSTART, 0);
 
-        uint32_t vlen = xc->readMiscReg(MISCREG_VLENB) * 8;
-        uint32_t vlmax = getVlmax(xc->readMiscReg(MISCREG_VTYPE), vlen);
-
         VTYPE new_vtype = requested_vtype;
-        if (xc->readMiscReg(MISCREG_VTYPE) != new_vtype) {
+        if (Vtype != new_vtype) {
             vlmax = getVlmax(new_vtype, vlen);
 
             float vflmul = getVflmul(new_vtype.vlmul);
@@ -68,17 +74,16 @@ def template VConfExecute {{
             uint32_t new_vill =
                 !(vflmul >= 0.125 && vflmul <= 8) ||
                     sew > std::min(vflmul, 1.0f) * ELEN ||
-                    bits(requested_vtype, 30, 8) != 0;
+                    bits(requested_vtype, 62, 8) != 0;
             if (new_vill) {
                 vlmax = 0;
                 new_vtype = 0;
                 new_vtype.vill = 1;
             }
-
-            xc->setMiscReg(MISCREG_VTYPE, new_vtype);
+        } else {
+            new_vtype = Vtype;
         }
 
-        uint32_t current_vl = xc->readMiscReg(MISCREG_VL);
         uint32_t new_vl = 0;
         if (vlmax == 0) {
             new_vl = 0;
@@ -90,11 +95,7 @@ def template VConfExecute {{
             new_vl = requested_vl > vlmax ? vlmax : requested_vl;
         }
 
-        xc->setMiscReg(MISCREG_VL, new_vl);
-
-        tc->getDecoderPtr()->as<Decoder>().setVlAndVtype(new_vl, new_vtype);
-
-        Rd = new_vl;
+        %(write_code)s;
 
         %(op_wb)s;
         return NoFault;

src/arch/riscv/isa/operands.isa

@@ -98,4 +98,10 @@ def operands {{
 #Program Counter Operands
     'PC': PCStateOp('ud', 'pc', (None, None, 'IsControl'), 7),
     'NPC': PCStateOp('ud', 'npc', (None, None, 'IsControl'), 8),
+
+# VL and VTYPE
+    'Vtype': PCStateOp('ud', 'vtype', (None, None, 'IsControl'), 10),
+    'VL': PCStateOp('uw', 'vl', (None, None, 'IsControl'), 11),
+#VLENB, actually the CSR is read only.
+    'VlenbBits': PCStateOp('ud', 'vlenb', (None, None, 'IsControl'), 12),
 }};