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gem5/src/arch/x86
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Gabe Black 5e1fdf7586 arch: Remove TheISA::VecElem from arch/vecregs.hh. 
Also remove unnecessary includes from the x86 version, and fix up
transitive includes from other x86 files.

Change-Id: I9f7d330f287c9ed52eed1544c47251b4354cfab3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49166
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-01 18:48:55 +00:00
..
bare_metal
arch-x86: Bare metal workload.
2022-01-15 08:40:06 +00:00
bios
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
insts
misc: Linearlize VecElem indexing.
2022-01-21 23:05:47 +00:00
isa
arch: Remove TheISA::VecElem from arch/vecregs.hh.
2022-02-01 18:48:55 +00:00
kvm
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
linux
arch: Remove TheISA::VecElem from arch/vecregs.hh.
2022-02-01 18:48:55 +00:00
regs
scons: Use tags to gate ISA files and not env['TARGET_ISA'].
2021-10-19 20:41:03 +00:00
AtomicSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
cpuid.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cpuid.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decoder_tables.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
decoder.cc
arch-x86: Use 16 bit modRM encoding if address size is 16 bit.
2022-01-15 07:59:41 +00:00
decoder.hh
arch,cpu: Turn the Decoder objects into SimObjects.
2021-12-06 03:09:22 +00:00
emulenv.cc
arch-x86: Handle a special case for MODRM in 16 bit mode.
2022-01-15 01:54:09 +00:00
emulenv.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
faults.cc
arch: Remove TheISA::VecElem from arch/vecregs.hh.
2022-02-01 18:48:55 +00:00
faults.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
fs_workload.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
fs_workload.hh
arch,sim: Add a byteOrder accessor to the Workload class.
2021-11-18 07:09:00 +00:00
interrupts.cc
arch: Remove TheISA::VecElem from arch/vecregs.hh.
2022-02-01 18:48:55 +00:00
interrupts.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
intmessage.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
isa.cc
arch,cpu: Stop using TheISA::Decoder in most places.
2021-12-06 03:09:22 +00:00
isa.hh
misc: Linearlize VecElem indexing.
2022-01-21 23:05:47 +00:00
ldstflags.hh
x86,mem: Replace the x86 StoreCheck flag with READ_MODIFY_WRITE.
2021-09-05 05:29:27 +00:00
memhelpers.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
microcode_rom.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mmu.hh
arch: Make the MMU ranged translateFunction pure virtual.
2021-10-22 21:43:02 +00:00
nativetrace.cc
misc: Stop including arch/pcstate.hh.
2021-11-30 23:30:06 +00:00
nativetrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
NonCachingSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
O3CPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
page_size.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable_walker.cc
arch: Remove TheISA::VecElem from arch/vecregs.hh.
2022-02-01 18:48:55 +00:00
pagetable_walker.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
pagetable.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pcstate.hh
arch,cpu: Make branching() a virtual member of PCStateBase.
2021-11-30 23:30:06 +00:00
process.cc
arch: Remove TheISA::VecElem from arch/vecregs.hh.
2022-02-01 18:48:55 +00:00
process.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pseudo_inst_abi.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
remote_gdb.cc
misc,cpu: Make ThreadContext work with PCStateBase-s.
2021-11-30 23:30:06 +00:00
remote_gdb.hh
base: Correct checkBpLen naming with checkBpKind
2021-12-16 13:26:39 +00:00
SConscript
arch-x86: Bare metal workload.
2022-01-15 08:40:06 +00:00
SConsopts
scons: Turn the ISA and GPU ISA lists into construction variables.
2021-08-07 03:12:56 +00:00
se_workload.hh
arch-x86: Make x86 respect m5op_base in SE mode.
2022-01-15 12:27:19 +00:00
stacktrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
TimingSimpleCPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
tlb.cc
arch,cpu: Stop using and remove ThreadContext::instAddr.
2021-11-30 23:30:06 +00:00
tlb.hh
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
types.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
types.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
utility.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
utility.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
vecregs.hh
arch: Remove TheISA::VecElem from arch/vecregs.hh.
2022-02-01 18:48:55 +00:00
x86_traits.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86CPU.py
cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.
2022-01-12 15:59:27 +00:00
X86Decoder.py
arch,cpu: Turn the Decoder objects into SimObjects.
2021-12-06 03:09:22 +00:00
X86FsWorkload.py
arch-x86: Bare metal workload.
2022-01-15 08:40:06 +00:00
X86ISA.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86LocalApic.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86MMU.py
arch: Add TypeTLB Param in BaseTLB
2021-07-28 08:13:09 +00:00
X86NativeTrace.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86SeWorkload.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
X86TLB.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00