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62e51987964b335757cc4f5af2fcf0161b07a599
gem5/src/mem
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Bobby R. Bruce d42eeb6b68 cpu: Explicitly define cache_line_size -> 64-bit unsigned int (#329) 
While it's plausible to define the cache_line_size as a 32-bit unsigned
int, the use of cache_line_size is way out of its original scope.

cache_line_size has been used to produce an address mask, which masking
out the offset bits from an address. For example, [1], [2], [3], and
[4]. However, since the cache_line_size is an "unsigned int", the type
of the value is not guaranteed to be 64-bit long. Subsequently, the bit
twiddling hacks in [1], [2], [3], and [4] produce 32-bit mask, i.e.,
0x00000000FFFFFFC0.

This behavior at least caused a problem in LLSC in RISC-V [5], where the
load reservation (LR) relies on the mask to produce the cache block
address. Two distinct 64-bit addresses can be mapped to the same cache
block using the above mask.

This patch explicitly defines cache_line_size as a 64-bit unsigned int
so the cache block mask can be produced correctly for 64-bit addresses.

[1]
3bdcfd6f7a/src/cpu/simple/atomic.hh (L147)
[2]
3bdcfd6f7a/src/cpu/simple/timing.hh (L224)
[3]
3bdcfd6f7a/src/cpu/o3/lsq_unit.cc (L241)
[4]
3bdcfd6f7a/src/cpu/minor/lsq.cc (L1425)
[5]
3bdcfd6f7a/src/arch/riscv/isa.cc (L787)
2023-10-16 07:50:35 -07:00
..
cache
misc,python: Run pre-commit run --all-files
2023-10-10 21:47:07 -07:00
probes
python: Fix multiline quotes in a single line
2022-11-29 23:44:38 +00:00
protocol
mem: Add an API for requesting a back door without a Packet/Request.
2022-11-22 04:56:14 +00:00
qos
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
ruby
mem-ruby: Always pass on GPU atomics to dir in write-through TCC (#367)
2023-10-14 06:39:50 -07:00
slicc
misc,python: Run pre-commit run --all-files
2023-10-10 21:47:07 -07:00
abstract_mem.cc
mem: Add a parameter which will make a memory truly a ROM.
2023-03-03 02:05:49 +00:00
abstract_mem.hh
mem: Add a parameter which will make a memory truly a ROM.
2023-03-03 02:05:49 +00:00
AbstractMemory.py
mem: Add a parameter which will make a memory truly a ROM.
2023-03-03 02:05:49 +00:00
addr_mapper.cc
mem: Support backdoor request in AddrMapper
2023-06-29 15:11:19 +00:00
addr_mapper.hh
mem: Support backdoor request in AddrMapper
2023-06-29 15:11:19 +00:00
AddrMapper.py
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
backdoor_manager.cc
mem: Support backdoor request in AddrMapper
2023-06-29 15:11:19 +00:00
backdoor_manager.hh
mem: Support backdoor request in AddrMapper
2023-06-29 15:11:19 +00:00
backdoor_manager.test.cc
mem: Support backdoor request in AddrMapper
2023-06-29 15:11:19 +00:00
backdoor.hh
mem: Add a class to describe a back door request.
2022-11-22 04:55:58 +00:00
bridge.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
bridge.hh
mem: Implemement backdoor interface for Bridge
2023-01-12 06:41:54 +00:00
Bridge.py
python: Fix multiline quotes in a single line
2022-11-29 23:44:38 +00:00
cfi_mem.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
cfi_mem.hh
dev,mem,systemc: Implement and use the recvMemBackdoorReq func.
2022-11-22 04:56:29 +00:00
CfiMemory.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
coherent_xbar.cc
mem: dump out port trace when address decode error
2023-08-15 00:41:42 -07:00
coherent_xbar.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
comm_monitor.cc
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
comm_monitor.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
CommMonitor.py
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
dram_interface.cc
mem: HBMCtrl changes to allow PC data buses to be in different states
2023-05-26 20:08:00 +00:00
dram_interface.hh
mem: Handle DRAM write queue drain and disabled power down
2023-05-25 19:14:46 +00:00
DRAMInterface.py
mem: Add a DDR5 memory interface
2023-05-26 03:58:44 +00:00
drampower.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
drampower.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dramsim2_wrapper.cc
misc: Rename DEBUG macro into GEM5_DEBUG
2023-03-21 06:53:55 +00:00
dramsim2_wrapper.hh
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
dramsim2.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
dramsim2.hh
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
dramsim3_wrapper.cc
misc: Rename DEBUG macro into GEM5_DEBUG
2023-03-21 06:53:55 +00:00
dramsim3_wrapper.hh
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
dramsim3.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
dramsim3.hh
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
DRAMsim3.py
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
DRAMSim2.py
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
dramsys_wrapper.cc
mem: Add DRAMSys wrapper as a memory object
2023-03-29 08:19:08 +00:00
dramsys_wrapper.hh
stdlib,configs: Add DRAMSys to the gem5 standard library
2023-03-29 08:19:08 +00:00
dramsys.hh
mem: Add DRAMSys wrapper as a memory object
2023-03-29 08:19:08 +00:00
DRAMSys.py
misc,python: Run pre-commit run --all-files
2023-10-10 21:47:07 -07:00
external_master.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
external_master.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
external_slave.cc
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
external_slave.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
ExternalMaster.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
ExternalSlave.py
python: Fix multiline quotes in a single line
2022-11-29 23:44:38 +00:00
hbm_ctrl.cc
mem: HBMCtrl changes to allow PC data buses to be in different states
2023-05-26 20:08:00 +00:00
hbm_ctrl.hh
mem: HBMCtrl changes to allow PC data buses to be in different states
2023-05-26 20:08:00 +00:00
HBMCtrl.py
mem: HBMCtrl changes to allow PC data buses to be in different states
2023-05-26 20:08:00 +00:00
hetero_mem_ctrl.cc
mem: Add an HBM memory controller
2022-06-06 18:31:06 +00:00
hetero_mem_ctrl.hh
mem: Add an HBM memory controller
2022-06-06 18:31:06 +00:00
HeteroMemCtrl.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
hmc_controller.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
hmc_controller.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
HMCController.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
htm.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
htm.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mem_checker_monitor.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mem_checker_monitor.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
mem_checker.cc
mem,sim: Replace the deprecated chatty_assert with gem5_assert.
2021-08-21 00:54:54 +00:00
mem_checker.hh
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
mem_ctrl.cc
mem: Make functional request a response when satisfied by queue
2023-07-26 17:34:24 +02:00
mem_ctrl.hh
mem: HBMCtrl changes to allow PC data buses to be in different states
2023-05-26 20:08:00 +00:00
mem_delay.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
mem_delay.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mem_interface.cc
mem: Add an HBM memory controller
2022-06-06 18:31:06 +00:00
mem_interface.hh
mem: HBMCtrl changes to allow PC data buses to be in different states
2023-05-26 20:08:00 +00:00
mem_requestor.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
MemChecker.py
python: Fix multiline quotes in a single line
2022-11-29 23:44:38 +00:00
MemCtrl.py
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
MemDelay.py
python: Fix multiline quotes in a single line
2022-11-29 23:44:38 +00:00
MemInterface.py
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
multi_level_page_table.hh
misc: Move MemPool based calls to the SEWorkload.
2021-09-21 02:05:32 +00:00
noncoherent_xbar.cc
mem: dump out port trace when address decode error
2023-08-15 00:41:42 -07:00
noncoherent_xbar.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
nvm_interface.cc
mem: HBMCtrl changes to allow PC data buses to be in different states
2023-05-26 20:08:00 +00:00
nvm_interface.hh
mem: Add an HBM memory controller
2022-06-06 18:31:06 +00:00
NVMInterface.py
misc: Run pre-commit run --all-files
2023-10-10 14:01:58 -07:00
packet_access.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
packet_queue.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
packet_queue.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
packet.cc
mem: introduce bad command error to packet commands
2022-11-01 05:51:20 +00:00
packet.hh
mem-cache: Fix another typo
2023-08-19 22:50:53 +00:00
page_table.cc
mem: Add a translation generator function to EmulationPageTable.
2021-10-22 21:43:02 +00:00
page_table.hh
mem: Add a translation generator function to EmulationPageTable.
2021-10-22 21:43:02 +00:00
physical.cc
mem: Align mmap offset to page boundary
2022-03-30 05:18:52 +00:00
physical.hh
mem: Align mmap offset to page boundary
2022-03-30 05:18:52 +00:00
port_proxy.cc
mem,sim: Change the type of cache_line_size to Addr
2023-09-20 14:00:45 -07:00
port_proxy.hh
mem,sim: Change the type of cache_line_size to Addr
2023-09-20 14:00:45 -07:00
port_terminator.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
port_terminator.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
port_wrapper.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
port_wrapper.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
port.cc
mem: port: add address value in the port trace
2023-08-15 00:38:29 -07:00
port.hh
mem: port: add getTraceInString() method
2023-08-15 00:40:29 -07:00
PortTerminator.py
python: Fix multiline quotes in a single line
2022-11-29 23:44:38 +00:00
qport.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
request.hh
tests,mem-ruby: Enhance ruby false sharing test with Atomics
2023-10-04 19:11:01 +02:00
SConscript
mem: Support backdoor request in AddrMapper
2023-06-29 15:11:19 +00:00
SConsopts
scons: Explicitly add librt to scons
2021-07-07 21:37:15 +00:00
se_translating_port_proxy.cc
mem: Use the MMU's translation generator in translating proxies.
2021-10-22 21:43:02 +00:00
se_translating_port_proxy.hh
mem: Use the MMU's translation generator in translating proxies.
2021-10-22 21:43:02 +00:00
serial_link.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
serial_link.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
SerialLink.py
python: Fix multiline quotes in a single line
2022-11-29 23:44:38 +00:00
shared_memory_server.cc
base: Update <experimental/filesystem> include
2023-04-24 23:30:01 +00:00
shared_memory_server.hh
mem: Use HostSocket in the SharedMemoryServer.
2023-04-11 07:34:32 +00:00
SharedMemoryServer.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
simple_mem.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
simple_mem.hh
dev,mem,systemc: Implement and use the recvMemBackdoorReq func.
2022-11-22 04:56:29 +00:00
SimpleMemory.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
snoop_filter.cc
mem: Fix 'unused variable' warnings
2022-10-10 17:24:03 +00:00
snoop_filter.hh
cpu,mem,dev: Use Addr for cacheLineSize
2023-09-20 14:16:46 -07:00
stack_dist_calc.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
stack_dist_calc.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
sys_bridge.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
sys_bridge.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
SysBridge.py
misc: Run pre-commit run on all files in repo
2022-08-24 21:47:07 +00:00
thread_bridge.cc
mem: use default backdoor behavior for thread_bridge
2023-02-08 00:27:54 +00:00
thread_bridge.hh
mem: use default backdoor behavior for thread_bridge
2023-02-08 00:27:54 +00:00
ThreadBridge.py
mem: implement ThreadBridge
2022-10-31 01:05:16 +00:00
token_port.cc
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
token_port.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
tport.cc
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
tport.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
translating_port_proxy.cc
mem: Fixing memory size type issue in port proxy.
2023-08-15 12:40:45 -07:00
translating_port_proxy.hh
mem: Fixing memory size type issue in port proxy.
2023-08-15 12:40:45 -07:00
translation_gen.hh
mem: Add a translation gen helper class.
2021-10-14 20:49:23 +00:00
translation_gen.test.cc
ext: upgrade to googletest 1.11.x
2022-01-20 01:16:02 +00:00
xbar.cc
mem: dump out port trace when address decode error
2023-08-15 00:41:42 -07:00
xbar.hh
mem: dump out port trace when address decode error
2023-08-15 00:41:42 -07:00
XBar.py
python: Fix multiline quotes in a single line
2022-11-29 23:44:38 +00:00