mem: Add a DDR5 memory interface
This change adds a single DDR5 memory inteface. A DDR5 DIMM contains two physical channels. Therefore, two instances of this interface should be used to model a DDR5 DIMM. The configuration includes 3 different speed bins models. The configuration is tested with different types of memory traffic using the traffic generator and shows performance similar to what is observed in existing literature [1]. One of the key features of DDR5 "same bank refresh" is yet not supported in gem5, but is expected to improve the performance of the DDR5 model. [1] Exploration of DDR5 with the Open-Source Simulator DRAMSys. Change-Id: I5856a10c8dcd92dbecc7fd4dcea0f674b2412dd7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68257 Maintainer: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Ayaz Akram
@@ -41,6 +41,7 @@
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from m5.objects.MemCtrl import MemCtrl
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from m5.objects.MemInterface import *
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# Enum for the page policy, either open, open_adaptive, close, or
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# close_adaptive.
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class PageManage(Enum):
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@@ -1179,7 +1180,6 @@ class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
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# on HBM gen2 specifications. 4H stack, 8Gb per die and total capacity
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# of 4GiB.
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class HBM_2000_4H_1x64(DRAMInterface):
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# 64-bit interface for a single pseudo channel
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device_bus_width = 64
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@@ -1256,6 +1256,268 @@ class HBM_2000_4H_1x64(DRAMInterface):
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two_cycle_activate = True
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# A single DDR5-4400 32bit channel (4x8 configuration)
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# A DDR5 DIMM is made up of two (32 bit) channels.
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# Following configuration is modeling only a single 32bit channel.
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# Timings are based on Micron data sheet:
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# https://media-www.micron.com/-/media/client/global/
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# documents/products/data-sheet/dram/ddr5/ddr5_sdram_core.pdf
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# Configuration: 4Gbx8 devices (32Gb addressing)
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# Maximum bandwidth of DDR5_4400_4x8 (4400 MT/s) can be 17.6GB/s
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class DDR5_4400_4x8(DRAMInterface):
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# size of a single device
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device_size = "512MiB"
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# single channel of 32bit width
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# requires 8-bit wide 4 devices
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device_bus_width = 8
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# DDR5 is a BL16 device
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burst_length = 16
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# Each device has a page (row buffer) size of 256B
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# Four devices lead to a page size of 1KB
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device_rowbuffer_size = "256B"
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# 4Gbx8 configuration
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devices_per_rank = 4
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ranks_per_channel = 1
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# 4Gbx8 configuration of DDR5 has 8 bank groups,
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# 4 banks per bank group and 32 banks in total
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bank_groups_per_rank = 8
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banks_per_rank = 32
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write_buffer_size = 64
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read_buffer_size = 64
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# For 4400 MT/s
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tCK = "0.454ns"
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# 16 beats across an x32 interface translates to 8 clocks @ 2200 MHz
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tBURST = "3.632ns"
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# For 4400 MT/s, the number is max(8nCK, 5ns)
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tCCD_L = "5ns"
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# page 389 of the data sheet
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tRCD = "14.545ns"
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tCL = "14.545ns"
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# tCWL = tCL - 2(nCK)
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tCWL = "13.637ns"
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tRP = "14.545ns"
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tRAS = "32ns"
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# RRD_S (different bank group) : 8nCK
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tRRD = "3.632ns"
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# RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page
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tRRD_L = "5ns"
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# tFAW for 1KB page is MAX(32nCK, 14.545ns)
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tXAW = "14.545ns"
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activation_limit = 4
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# Note: could not find the rank to rank delay
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# from the datasheet, but, since we are modeling
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# a single rank device, it should not matter.
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# Using the DDR4 number as default (i.e. ~2tCK)
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tCS = "1ns"
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# tRFC (Normal) for 16Gb device is 295ns
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tRFC = "295ns"
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tPPD = "0.908ns" # 2nCK
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tWR = "30ns"
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# Rd/Wr turnaround timings
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###################################################################
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# Note: gem5 adds tBURST separately while calculting rd--rd/wr or
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# wr--wr/rd delays so we can ignore tBURST factor from the following
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# equations while calculating the final value of the timing parameter
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####################################################################
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# From the datasheet
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# (1) tCCD_L_RTW =
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# CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE
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# where CWL = CL-2, RBL/2 = tBURST, Read DQS offset = 1ck, tRPST = 1.5tCK
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# Therefore, tCCD_L_RTW =
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# (14.545 - 13.637) + (2*0.454) - 0.454 +
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# ((1.5*0.454)-(0.5*0.454) + (1.5*0.454) = 2.497ns
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# (2) tCCD_S_RTW =
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# CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE
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# Therefore, tCCD_S_RTW = tCCD_L_RTW = 2.497ns
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# (3) tCCD_L_WTR =
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# CWL + WBL/2 + max(16nCK,10ns)
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# where WBL/2 = tBURST
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# Therefore,
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# tCCD_L_WTR = 13.637+10 = 23.637ns
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# (4) tCCD_S_WTR =
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# CWL + WBL/2 + max(4nCK,2.5ns)
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# where WBL/2 = tBURST
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# Therefore,
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# tCCD_S_WTR = 13.637+2.5 = 16.137ns
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tRTW = "2.497ns"
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tWTR_L = "23.637ns"
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tWTR = "16.137ns"
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# tRTP : max(12nCK, 7.5ns)
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tRTP = "7.5ns"
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# <=85C, half for >85C
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tREFI = "3.9us"
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# active powerdown and precharge powerdown exit time max(7.5ns, 8nCK)
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tXP = "7.5ns"
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# self refresh exit time
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# According to the datasheet tXS = tRFC = 295ns (normal Refresh mode)
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tXS = "295ns"
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page_policy = "close_adaptive"
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# Power related parameters
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# Reference: https://media-www.micron.com/-/media/client/global/
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# documents/products/data-sheet/dram/ddr5/16gb_ddr5_sdram_diereva.pdf
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# Using the values for DDR5-4800
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# DDR5 has one voltage domain, so all the
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# CurrentVariable2 params should not be used or set to 0
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IDD0 = "122mA"
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# Using the value of IDD2P
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IDD2P0 = "88mA"
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IDD2N = "92mA"
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# Using the value of IDD3P
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IDD3P0 = "140mA"
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IDD3N = "142mA"
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IDD4W = "479mA"
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IDD4R = "530mA"
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# IDD5B - 277, IDD5C -- 135mA, IDD5F -- 262mA in the datasheet
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IDD5 = "277mA"
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# IDD6N
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IDD6 = "102mA"
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VDD = "1.1V"
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# Maximum bandwidth of DDR5_6400_4x8 (6400 MT/s) can be 25.6GB/s
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class DDR5_6400_4x8(DDR5_4400_4x8):
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# For 6400 MT/s
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tCK = "0.312ns"
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# 16 beats across an x32 interface translates to 8 clocks @ 3200 MHz
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tBURST = "2.496ns"
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tRCD = "14.375ns"
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tCL = "14.375ns"
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# tCWL = tCL - 2(nCK)
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tCWL = "13.751ns"
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tRP = "14.375ns"
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# RRD_S (different bank group) : 8nCK
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tRRD = "2.496ns"
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# RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page
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tRRD_L = "5ns"
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# tFAW for 1KB page is MAX(32 CK, 10.00ns)
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tXAW = "10ns"
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# Rd/Wr turnaround timings
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###################################################################
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# Note: gem5 adds tBURST separately while calculting rd--rd/wr or
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# wr--wr/rd delays so we can ignore tBURST factor from the following
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# equations while calculating the final value of the timing parameter
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####################################################################
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# From the datasheet
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# (1) tCCD_L_RTW =
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# CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE
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# where CWL = CL-2, RBL/2 = tBURST, Read DQS offset = 1ck, tRPST = 1.5tCK
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# Therefore, tCCD_L_RTW =
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# (14.375 - 13.751) + (2*0.312) - 0.312 + ((1.5*0.312)-(0.5*0.312)
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# + (1.5*0.312) = 1.716ns
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# (2) tCCD_S_RTW =
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# CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE
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# Therefore, tCCD_S_RTW = tCCD_L_RTW = 1.716ns
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# (3) tCCD_L_WTR =
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# CWL + WBL/2 + max(16nCK,10ns)
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# where WBL/2 = tBURST
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# Therefore,
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# tCCD_L_WTR = 13.751+10 = 23.751ns
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# (4) tCCD_S_WTR =
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# CWL + WBL/2 + max(4nCK,2.5ns)
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# where WBL/2 = tBURST
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# Therefore,
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# tCCD_S_WTR = 13.751+2.5 = 16.251ns
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tRTW = "1.716ns"
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tWTR_L = "23.751ns"
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tWTR = "16.251ns"
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# Maximum bandwidth of DDR5_8400_4x8 (8400 MT/s) can be 33.6GB/s
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# Most of the timing parameters for DDR5_8400_4x8 are TBD in
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# the datasheet referred above.
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# The TBD parameters are extrapolated from the speed bins mentioned above.
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class DDR5_8400_4x8(DDR5_4400_4x8):
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# For 8400 MT/s
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tCK = "0.238ns"
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# 16 beats across an x32 interface translates to 8 clocks @ 4200 MHz
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tBURST = "1.904ns"
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tRCD = "14.285ns"
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tCL = "14.285ns"
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tCWL = "13.809ns"
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tRP = "14.285ns"
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# RRD_S (different bank group) : 8nCK
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tRRD = "1.904ns"
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# tFAW for 1KB page is MAX(32 CK, 10.00ns)
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tXAW = "10ns"
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# Rd/Wr turnaround timings
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###################################################################
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# Note: gem5 adds tBURST separately while calculting rd--rd/wr or
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# wr--wr/rd delays so we can ignore tBURST factor from the following
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# equations while calculating the final value of the timing parameter
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####################################################################
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# From the datasheet
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# (1) tCCD_L_RTW =
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# CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE
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# where CWL = CL-2, RBL/2 = tBURST, Read DQS offset = 1ck, tRPST = 1.5tCK
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# Therefore, tCCD_L_RTW =
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# (14.285 - 13.809) + (2*0.238) - 0.238 + ((1.5*0.238)-(0.5*0.238)
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# + (1.5*0.238) = 1.309ns
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# (2) tCCD_S_RTW =
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# CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE
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# Therefore, tCCD_S_RTW = tCCD_L_RTW = 1.309ns
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# (3) tCCD_L_WTR =
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# CWL + WBL/2 + max(16nCK,10ns)
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# where WBL/2 = tBURST
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# Therefore,
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# tCCD_L_WTR =13.809+10 = 23.809ns
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# (4) tCCD_S_WTR =
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# CWL + WBL/2 + max(4nCK,2.5ns)
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# where WBL/2 = tBURST
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# Therefore,
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# tCCD_S_WTR = 13.809+2.5 = 16.309ns
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tRTW = "1.309ns"
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tWTR_L = "23.809ns"
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tWTR = "16.309ns"
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# A single LPDDR5 x16 interface (one command/address bus)
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# for a single x16 channel with default timings based on
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# initial JEDEC specification
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@@ -1263,7 +1525,6 @@ class HBM_2000_4H_1x64(DRAMInterface):
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# Configuring for 16-bank mode with bank-group architecture
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# burst of 32, which means bursts can be interleaved
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class LPDDR5_5500_1x16_BG_BL32(DRAMInterface):
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# Increase buffer size to account for more bank resources
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read_buffer_size = 64
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@@ -1390,7 +1651,6 @@ class LPDDR5_5500_1x16_BG_BL32(DRAMInterface):
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# Starting with 5.5Gbps data rates and 8Gbit die
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# Configuring for 16-bank mode with bank-group architecture, burst of 16
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class LPDDR5_5500_1x16_BG_BL16(LPDDR5_5500_1x16_BG_BL32):
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# LPDDR5 is a BL16 or BL32 device
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# With BG mode, BL16 and BL32 are supported
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# Use BL16 for smaller access granularity
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@@ -1412,7 +1672,6 @@ class LPDDR5_5500_1x16_BG_BL16(LPDDR5_5500_1x16_BG_BL32):
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# Starting with 5.5Gbps data rates and 8Gbit die
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# Configuring for 8-bank mode, burst of 32
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class LPDDR5_5500_1x16_8B_BL32(LPDDR5_5500_1x16_BG_BL32):
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# 4KiB page with 8B mode
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device_rowbuffer_size = "4KiB"
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@@ -1452,7 +1711,6 @@ class LPDDR5_5500_1x16_8B_BL32(LPDDR5_5500_1x16_BG_BL32):
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# Configuring for 16-bank mode with bank-group architecture
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# burst of 32, which means bursts can be interleaved
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class LPDDR5_6400_1x16_BG_BL32(LPDDR5_5500_1x16_BG_BL32):
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# 5.5Gb/s DDR with 4:1 WCK:CK ratio for 687.5 MHz CK
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tCK = "1.25ns"
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@@ -1497,7 +1755,6 @@ class LPDDR5_6400_1x16_BG_BL32(LPDDR5_5500_1x16_BG_BL32):
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# 6.4Gbps data rates and 8Gbit die
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# Configuring for 16-bank mode with bank-group architecture, burst of 16
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class LPDDR5_6400_1x16_BG_BL16(LPDDR5_6400_1x16_BG_BL32):
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# LPDDR5 is a BL16 or BL32 device
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# With BG mode, BL16 and BL32 are supported
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# Use BL16 for smaller access granularity
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@@ -1519,7 +1776,6 @@ class LPDDR5_6400_1x16_BG_BL16(LPDDR5_6400_1x16_BG_BL32):
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# 6.4Gbps data rates and 8Gbit die
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# Configuring for 8-bank mode, burst of 32
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class LPDDR5_6400_1x16_8B_BL32(LPDDR5_6400_1x16_BG_BL32):
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# 4KiB page with 8B mode
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device_rowbuffer_size = "4KiB"
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@@ -185,6 +185,8 @@ PySource('gem5.components.memory.dram_interfaces',
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'gem5/components/memory/dram_interfaces/ddr3.py')
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PySource('gem5.components.memory.dram_interfaces',
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'gem5/components/memory/dram_interfaces/ddr4.py')
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PySource('gem5.components.memory.dram_interfaces',
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'gem5/components/memory/dram_interfaces/ddr5.py')
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PySource('gem5.components.memory.dram_interfaces',
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'gem5/components/memory/dram_interfaces/gddr.py')
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PySource('gem5.components.memory.dram_interfaces',
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@@ -29,6 +29,9 @@ from .single_channel import SingleChannelDDR3_2133
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from .single_channel import SingleChannelDDR4_2400
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from .single_channel import SingleChannelHBM
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from .single_channel import SingleChannelLPDDR3_1600
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from .single_channel import DIMM_DDR5_4400
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from .single_channel import DIMM_DDR5_6400
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from .single_channel import DIMM_DDR5_8400
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from .multi_channel import DualChannelDDR3_1600
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from .multi_channel import DualChannelDDR3_2133
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from .multi_channel import DualChannelDDR4_2400
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292
src/python/gem5/components/memory/dram_interfaces/ddr5.py
Normal file
292
src/python/gem5/components/memory/dram_interfaces/ddr5.py
Normal file
@@ -0,0 +1,292 @@
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# Copyright (c) 2023 The Regents of the University of California
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# All Rights Reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""Interfaces for DDR5 memories
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"""
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from m5.objects import DRAMInterface
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|
||||
# A single DDR5-4400 32bit channel (4x8 configuration)
|
||||
# A DDR5 DIMM is made up of two (32 bit) channels.
|
||||
# Following configuration is modeling only a single 32bit channel.
|
||||
# Timings are based on Micron data sheet:
|
||||
# https://media-www.micron.com/-/media/client/global/
|
||||
# documents/products/data-sheet/dram/ddr5/ddr5_sdram_core.pdf
|
||||
# Configuration: 4Gbx8 devices (32Gb addressing)
|
||||
# Maximum bandwidth of DDR5_4400_4x8 (4400 MT/s) can be 17.6GB/s
|
||||
class DDR5_4400_4x8(DRAMInterface):
|
||||
# size of a single device
|
||||
device_size = "512MiB"
|
||||
|
||||
# single channel of 32bit width
|
||||
# requires 8-bit wide 4 devices
|
||||
device_bus_width = 8
|
||||
|
||||
# DDR5 is a BL16 device
|
||||
burst_length = 16
|
||||
|
||||
# Each device has a page (row buffer) size of 256B
|
||||
# Four devices lead to a page size of 1KB
|
||||
device_rowbuffer_size = "256B"
|
||||
|
||||
# 4Gbx8 configuration
|
||||
devices_per_rank = 4
|
||||
|
||||
ranks_per_channel = 1
|
||||
|
||||
# 4Gbx8 configuration of DDR5 has 8 bank groups,
|
||||
# 4 banks per bank group and 32 banks in total
|
||||
bank_groups_per_rank = 8
|
||||
banks_per_rank = 32
|
||||
|
||||
write_buffer_size = 64
|
||||
read_buffer_size = 64
|
||||
|
||||
# For 4400 MT/s
|
||||
tCK = "0.454ns"
|
||||
|
||||
# 16 beats across an x32 interface translates to 8 clocks @ 2200 MHz
|
||||
tBURST = "3.632ns"
|
||||
|
||||
# For 4400 MT/s, the number is max(8nCK, 5ns)
|
||||
tCCD_L = "5ns"
|
||||
|
||||
# page 389 of the data sheet
|
||||
tRCD = "14.545ns"
|
||||
tCL = "14.545ns"
|
||||
# tCWL = tCL - 2(nCK)
|
||||
tCWL = "13.637ns"
|
||||
tRP = "14.545ns"
|
||||
tRAS = "32ns"
|
||||
|
||||
# RRD_S (different bank group) : 8nCK
|
||||
tRRD = "3.632ns"
|
||||
|
||||
# RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page
|
||||
tRRD_L = "5ns"
|
||||
|
||||
# tFAW for 1KB page is MAX(32nCK, 14.545ns)
|
||||
tXAW = "14.545ns"
|
||||
activation_limit = 4
|
||||
|
||||
# Note: could not find the rank to rank delay
|
||||
# from the datasheet, but, since we are modeling
|
||||
# a single rank device, it should not matter.
|
||||
# Using the DDR4 number as default (i.e. ~2tCK)
|
||||
tCS = "1ns"
|
||||
|
||||
# tRFC (Normal) for 16Gb device is 295ns
|
||||
tRFC = "295ns"
|
||||
|
||||
tPPD = "0.908ns" # 2nCK
|
||||
tWR = "30ns"
|
||||
|
||||
# Rd/Wr turnaround timings
|
||||
###################################################################
|
||||
# Note: gem5 adds tBURST separately while calculting rd--rd/wr or
|
||||
# wr--wr/rd delays so we can ignore tBURST factor from the following
|
||||
# equations while calculating the final value of the timing parameter
|
||||
####################################################################
|
||||
# From the datasheet
|
||||
# (1) tCCD_L_RTW =
|
||||
# CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE
|
||||
# where CWL = CL-2, RBL/2 = tBURST, Read DQS offset = 1ck, tRPST = 1.5tCK
|
||||
# Therefore, tCCD_L_RTW =
|
||||
# (14.545 - 13.637) + (2*0.454) - 0.454 +
|
||||
# ((1.5*0.454)-(0.5*0.454) + (1.5*0.454) = 2.497ns
|
||||
|
||||
# (2) tCCD_S_RTW =
|
||||
# CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE
|
||||
# Therefore, tCCD_S_RTW = tCCD_L_RTW = 2.497ns
|
||||
|
||||
# (3) tCCD_L_WTR =
|
||||
# CWL + WBL/2 + max(16nCK,10ns)
|
||||
# where WBL/2 = tBURST
|
||||
# Therefore,
|
||||
# tCCD_L_WTR = 13.637+10 = 23.637ns
|
||||
|
||||
# (4) tCCD_S_WTR =
|
||||
# CWL + WBL/2 + max(4nCK,2.5ns)
|
||||
# where WBL/2 = tBURST
|
||||
# Therefore,
|
||||
# tCCD_S_WTR = 13.637+2.5 = 16.137ns
|
||||
|
||||
tRTW = "2.497ns"
|
||||
tWTR_L = "23.637ns"
|
||||
tWTR = "16.137ns"
|
||||
|
||||
# tRTP : max(12nCK, 7.5ns)
|
||||
tRTP = "7.5ns"
|
||||
|
||||
# <=85C, half for >85C
|
||||
tREFI = "3.9us"
|
||||
|
||||
# active powerdown and precharge powerdown exit time max(7.5ns, 8nCK)
|
||||
tXP = "7.5ns"
|
||||
|
||||
# self refresh exit time
|
||||
# According to the datasheet tXS = tRFC = 295ns (normal Refresh mode)
|
||||
tXS = "295ns"
|
||||
|
||||
page_policy = "close_adaptive"
|
||||
|
||||
# Power related parameters
|
||||
# Reference: https://media-www.micron.com/-/media/client/global/
|
||||
# documents/products/data-sheet/dram/ddr5/16gb_ddr5_sdram_diereva.pdf
|
||||
# Using the values for DDR5-4800
|
||||
# DDR5 has one voltage domain, so all the
|
||||
# CurrentVariable2 params should not be used or set to 0
|
||||
IDD0 = "122mA"
|
||||
# Using the value of IDD2P
|
||||
IDD2P0 = "88mA"
|
||||
IDD2N = "92mA"
|
||||
# Using the value of IDD3P
|
||||
IDD3P0 = "140mA"
|
||||
IDD3N = "142mA"
|
||||
IDD4W = "479mA"
|
||||
IDD4R = "530mA"
|
||||
# IDD5B - 277, IDD5C -- 135mA, IDD5F -- 262mA in the datasheet
|
||||
IDD5 = "277mA"
|
||||
# IDD6N
|
||||
IDD6 = "102mA"
|
||||
|
||||
VDD = "1.1V"
|
||||
|
||||
|
||||
# Maximum bandwidth of DDR5_6400_4x8 (6400 MT/s) can be 25.6GB/s
|
||||
class DDR5_6400_4x8(DDR5_4400_4x8):
|
||||
# For 6400 MT/s
|
||||
tCK = "0.312ns"
|
||||
|
||||
# 16 beats across an x32 interface translates to 8 clocks @ 3200 MHz
|
||||
tBURST = "2.496ns"
|
||||
|
||||
tRCD = "14.375ns"
|
||||
tCL = "14.375ns"
|
||||
# tCWL = tCL - 2(nCK)
|
||||
tCWL = "13.751ns"
|
||||
tRP = "14.375ns"
|
||||
|
||||
# RRD_S (different bank group) : 8nCK
|
||||
tRRD = "2.496ns"
|
||||
|
||||
# RRD_L (same bank group) is MAX(8nCK, 5ns) for 1KB page
|
||||
tRRD_L = "5ns"
|
||||
|
||||
# tFAW for 1KB page is MAX(32 CK, 10.00ns)
|
||||
tXAW = "10ns"
|
||||
|
||||
# Rd/Wr turnaround timings
|
||||
###################################################################
|
||||
# Note: gem5 adds tBURST separately while calculting rd--rd/wr or
|
||||
# wr--wr/rd delays so we can ignore tBURST factor from the following
|
||||
# equations while calculating the final value of the timing parameter
|
||||
####################################################################
|
||||
# From the datasheet
|
||||
# (1) tCCD_L_RTW =
|
||||
# CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE
|
||||
# where CWL = CL-2, RBL/2 = tBURST, Read DQS offset = 1ck, tRPST = 1.5tCK
|
||||
# Therefore, tCCD_L_RTW =
|
||||
# (14.375 - 13.751) + (2*0.312) - 0.312 + ((1.5*0.312)-(0.5*0.312)
|
||||
# + (1.5*0.312) = 1.716ns
|
||||
|
||||
# (2) tCCD_S_RTW =
|
||||
# CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE
|
||||
# Therefore, tCCD_S_RTW = tCCD_L_RTW = 1.716ns
|
||||
|
||||
# (3) tCCD_L_WTR =
|
||||
# CWL + WBL/2 + max(16nCK,10ns)
|
||||
# where WBL/2 = tBURST
|
||||
# Therefore,
|
||||
# tCCD_L_WTR = 13.751+10 = 23.751ns
|
||||
|
||||
# (4) tCCD_S_WTR =
|
||||
# CWL + WBL/2 + max(4nCK,2.5ns)
|
||||
# where WBL/2 = tBURST
|
||||
# Therefore,
|
||||
# tCCD_S_WTR = 13.751+2.5 = 16.251ns
|
||||
|
||||
tRTW = "1.716ns"
|
||||
tWTR_L = "23.751ns"
|
||||
tWTR = "16.251ns"
|
||||
|
||||
|
||||
# Maximum bandwidth of DDR5_8400_4x8 (8400 MT/s) can be 33.6GB/s
|
||||
# Most of the timing parameters for DDR5_8400_4x8 are TBD in
|
||||
# the datasheet referred above.
|
||||
# The TBD parameters are extrapolated from the speed bins mentioned above.
|
||||
class DDR5_8400_4x8(DDR5_4400_4x8):
|
||||
# For 8400 MT/s
|
||||
tCK = "0.238ns"
|
||||
|
||||
# 16 beats across an x32 interface translates to 8 clocks @ 4200 MHz
|
||||
tBURST = "1.904ns"
|
||||
|
||||
tRCD = "14.285ns"
|
||||
tCL = "14.285ns"
|
||||
tCWL = "13.809ns"
|
||||
tRP = "14.285ns"
|
||||
|
||||
# RRD_S (different bank group) : 8nCK
|
||||
tRRD = "1.904ns"
|
||||
|
||||
# tFAW for 1KB page is MAX(32 CK, 10.00ns)
|
||||
tXAW = "10ns"
|
||||
|
||||
# Rd/Wr turnaround timings
|
||||
###################################################################
|
||||
# Note: gem5 adds tBURST separately while calculting rd--rd/wr or
|
||||
# wr--wr/rd delays so we can ignore tBURST factor from the following
|
||||
# equations while calculating the final value of the timing parameter
|
||||
####################################################################
|
||||
# From the datasheet
|
||||
# (1) tCCD_L_RTW =
|
||||
# CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE
|
||||
# where CWL = CL-2, RBL/2 = tBURST, Read DQS offset = 1ck, tRPST = 1.5tCK
|
||||
# Therefore, tCCD_L_RTW =
|
||||
# (14.285 - 13.809) + (2*0.238) - 0.238 + ((1.5*0.238)-(0.5*0.238)
|
||||
# + (1.5*0.238) = 1.309ns
|
||||
|
||||
# (2) tCCD_S_RTW =
|
||||
# CL - CWL + RBL/2 + 2 tCK - (Read DQS offset) + (tRPST - 0.5 tCK) + tWPRE
|
||||
# Therefore, tCCD_S_RTW = tCCD_L_RTW = 1.309ns
|
||||
|
||||
# (3) tCCD_L_WTR =
|
||||
# CWL + WBL/2 + max(16nCK,10ns)
|
||||
# where WBL/2 = tBURST
|
||||
# Therefore,
|
||||
# tCCD_L_WTR =13.809+10 = 23.809ns
|
||||
|
||||
# (4) tCCD_S_WTR =
|
||||
# CWL + WBL/2 + max(4nCK,2.5ns)
|
||||
# where WBL/2 = tBURST
|
||||
# Therefore,
|
||||
# tCCD_S_WTR = 13.809+2.5 = 16.309ns
|
||||
|
||||
tRTW = "1.309ns"
|
||||
tWTR_L = "23.809ns"
|
||||
tWTR = "16.309ns"
|
||||
@@ -29,6 +29,7 @@ from .abstract_memory_system import AbstractMemorySystem
|
||||
|
||||
from typing import Optional
|
||||
|
||||
from .dram_interfaces.ddr5 import DDR5_4400_4x8, DDR5_6400_4x8, DDR5_8400_4x8
|
||||
from .dram_interfaces.ddr4 import DDR4_2400_8x8
|
||||
from .dram_interfaces.hbm import HBM_1000_4H_1x128
|
||||
from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32
|
||||
@@ -74,3 +75,30 @@ def SingleChannelHBM(
|
||||
if not size:
|
||||
size = "256MiB"
|
||||
return ChanneledMemory(HBM_1000_4H_1x128, 1, 64, size=size)
|
||||
|
||||
|
||||
def DIMM_DDR5_4400(
|
||||
size: Optional[str] = None,
|
||||
) -> AbstractMemorySystem:
|
||||
"""
|
||||
A single DIMM of DDR5 has two channels
|
||||
"""
|
||||
return ChanneledMemory(DDR5_4400_4x8, 2, 64, size=size)
|
||||
|
||||
|
||||
def DIMM_DDR5_6400(
|
||||
size: Optional[str] = None,
|
||||
) -> AbstractMemorySystem:
|
||||
"""
|
||||
A single DIMM of DDR5 has two channels
|
||||
"""
|
||||
return ChanneledMemory(DDR5_6400_4x8, 2, 64, size=size)
|
||||
|
||||
|
||||
def DIMM_DDR5_8400(
|
||||
size: Optional[str] = None,
|
||||
) -> AbstractMemorySystem:
|
||||
"""
|
||||
A single DIMM of DDR5 has two channels
|
||||
"""
|
||||
return ChanneledMemory(DDR5_8400_4x8, 2, 64, size=size)
|
||||
|
||||
Reference in New Issue
Block a user