Hoa Nguyen c3acfdc9b8 arch-riscv: Copy Misc Regs when swiching cpus (#479) ...

Misc Regs might contain rather important information about the state of
a core, e.g., information in CSR registers.

This patch enforces copying the CSR registers when switching cpus. The
bug and the proposed fix are reported here [1].

[1] https://github.com/gem5/gem5/issues/451

Change-Id: I611782e6e3bcd5530ddac346342a9e0e44b0f757

Signed-off-by: Hoa Nguyen <hn@hnpl.org>

2023-10-18 10:51:37 -07:00

..

arch

arch-riscv: Copy Misc Regs when swiching cpus (#479)

2023-10-18 10:51:37 -07:00

base

misc: Run pre-commit run --all-files

2023-10-10 14:01:58 -07:00

cpu

tests: Changed percent atomics to 0 in memtest to fix daily test (#477)

2023-10-18 10:09:45 -07:00

dev

arch-riscv: Add bootloader+kernel workload (#390)

2023-10-18 09:17:12 -07:00

doc

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doxygen

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gpu-compute

gpu-compute: Update tokens for flat global/scratch (#408)

2023-10-11 09:00:10 -07:00

kern

misc: Fix buggy special path comparisons

2023-09-05 13:44:10 -07:00

learning_gem5

cpu: Explicitly define cache_line_size -> 64-bit unsigned int (#329)

2023-10-16 07:50:35 -07:00

mem

cpu: Explicitly define cache_line_size -> 64-bit unsigned int (#329)

2023-10-16 07:50:35 -07:00

proto

scons: Use pkgconfig to get correct Protobuf dependency (#68)

2023-07-17 15:29:05 -07:00

python

arch-riscv: Add bootloader+kernel workload (#390)

2023-10-18 09:17:12 -07:00

sim

cpu: Explicitly define cache_line_size -> 64-bit unsigned int (#329)

2023-10-16 07:50:35 -07:00

sst

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

2023-02-03 06:11:45 +00:00

systemc

misc: fix clang13 overloaded-virtual warning (#454)

2023-10-16 07:23:08 -07:00

Doxyfile

misc: Update version info for develop branch

2023-07-10 12:28:44 -07:00

SConscript

python: Add importer to standalone gem5py_m5

2023-09-28 11:22:33 -07:00