Commit Graph

180 Commits

Author SHA1 Message Date
Giacomo Travaglini
458c98082c arch-arm: Replace EL based translation with regimes
This is the final step in the transformation process.
We limit the use of the "managing Exception Level" for
a translation in favour of the more standard "Translation
Regime"
This greatly simplifies our code, especially with VHE
where the managing el (EL2) could handle to different
translation regimes (EL and EL2&0).

We can therefore remove the isHost flag wherever it got
used. That case is automatically handled by the proper
regime value (EL2&0)

Change-Id: Iafd1d2ce4757cfa6598656759694e5e7b05267ad
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2024-02-01 13:43:47 +00:00
Giacomo Travaglini
594428f010 arch-arm: Remove redundant isHyp as a TLB entry field
We should stop using isHyp.. An hypervisor entry is flagged
already by the EL of the entry (el == EL2)

Change-Id: I20c3d06fa2b04e0b938a380ca917d0b596eddcf2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2024-02-01 13:43:00 +00:00
Giacomo Travaglini
174adc2993 arch-arm: Revamp TLB invalidation by introducing TLBIOp::match
Most of the invalidation methods in the TLB class are
doing the same thing: looping over all entries, checking if
the entry matches a certain criteria, and invalidating it
in case it does.

The only specific bit is the matching function, therefore
we add a virtual TLBIOp::match method which allows us
to specialize different TLBIs and to provide a single
flush method in the TLB class

Change-Id: I0672ff958742ac7ebff8d30218f75127343f1a58
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61753
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
2022-07-30 08:59:49 +00:00
Giacomo Travaglini
1290d15973 arch-arm: Simplify TLB invalidation with flushMva
The method is no longer calling the lookup method which
had been complicated by the introduction of partial translations.
(which is now called during address translation only)

The lookup method is iterating over all TLB Entries until a non
partial translation is found. Using lookup in flushMva makes it
O(n^2). With this patch we iterate over the TLB entries only once
(making flushMva O(n))

Change-Id: I8f2ae56192812cee231baf6943068abea4d7ef91
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61752
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-07-30 08:59:49 +00:00
Giacomo Travaglini
49cb833ee6 arch-arm: Allow TLB to be used as a WalkCache
This patch allows partial translation entries (intermediate PAs obtained
from a table walk) to be stored in an ArmTLB. This effectively means
reserving a fraction of the TLB entries to cache table walks

JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: Id0efb7d75dd017366c4c3b74de7b57355a53a01a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52124
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-12 05:04:24 +00:00
Giacomo Travaglini
6c9792d333 arch-arm: EL2&0 invalidations do not depend on VMID
When the PE is executing in host mode (HCR.E2H = HCR.TGE = 1)
The invalidation shouldn't depend on the current VMID

Change-Id: I3433485cc8f8dedb657139bcc3d71e05e9d7e4f1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51671
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-10-18 13:47:18 +00:00
Giacomo Travaglini
f49a15e00f arch-arm: Define a Lookup structure to simplify TLB code
The lookup/matching function signatures have been constantly amended to
include new parameters. We are replacing the parameter list with a
single lookup structure. This will make it easier to add new forms of
lookups and to propagate them through the MMU/TLB code

Change-Id: Ic45a64d778460b6d308551333c9dc230a02ecb6e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51669
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-10-18 13:47:18 +00:00
Giacomo Travaglini
8fe7a740e3 arch-arm: Do not always print 0 stats in ArmTLB
We shouldn't print all TLB stats regardless of their value

For example there is no need to print the number of
read/write hits/misses/accesses in a instruction only TLB as
it will always inevitably be zero

With this patch we are flagging them as nozero, in order
to suppress their printing in the final stats file.
We are still printing them (regardless of their value) in the
unified TLB type

Change-Id: I54e57d856ceb451f6bacdd175a61768d030862aa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51667
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-18 13:47:18 +00:00
Giacomo Travaglini
fb0929b5f9 arch-arm: Provide support for a multilevel-TLB in the ArmMMU
This is an initial implementation. It adapts the current MMU code
to account for extra levels of TLBs but it is still missing the
configurability we are looking for (to select the associativity
of the TLB and the replacement policy as an example)

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I938ec38183337cd0e839bf3e3cd03594126128cd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48149
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-08-05 08:26:33 +00:00
Giacomo Travaglini
395c6d4fa3 arch-arm: Explicitly implement I/DTLBI Ops in TLB
At the moment the ITLBI and DTLBI operations where implicitly
implemented as generic TLBIs

e.g:

* DTLBIASID, ITLBIASID = TLBIASID

This was possible as a single TLB was either an instruction TLB
or a data TLB and no generic/shared TLB option was available.
In other words, an ITLBI Op to an ITB was invalidating all entries
as we were sure the ITB was not containing data entries.

With shared TLBs, this doesn't hold true and we need to explicitly
implement I/DTLBIs

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I39a4add7674f6008dacaedfd1fd90560d264048e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48148
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-08-05 08:26:33 +00:00
Giacomo Travaglini
1320dc4278 arch-arm: Remove unused parameter from TLB::insert
Change-Id: Iab395834fe8b3fabf4f5f666af1b8790af08182d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48144
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-07-28 08:13:09 +00:00
Giacomo Travaglini
870f93301f arch-arm: Move translation logic from the ArmTLB to the ArmMMU
This patch is moving most of the TLB code to the MMU.
In this way the TLB stops being the main translating agent and becomes a
simple "passive" translation cache.

All the logic behind virtual memory translation, like

* Checking permission/alignment
* Issuing page table walks
* etc

Is now embedded in the MMU model. This will allow us to stack multiple
TLBs and to compose arbitrary hierarchies as their sole purpose now is
to cache translations

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I687c639a56263d5e3bb6633dd8c9666c85edba3a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48141
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-28 08:13:09 +00:00
Gabe Black
cb266a099f misc: Replace GEM5_FALLTHROUGH with [[fallthrough]].
Now that the [[fallthrough]] attribute is standard (as of c++-17), we
can use it directly instead of hiding it behind a macro.

Change-Id: I4d11e35b619532b1a3fd8d042265e18c80d86f9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48505
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-24 21:57:04 +00:00
Richard Cooper
c25ef2d191 arch-arm: Update ARMv8.1-PAN to allow unprivileged instructions.
Update the ARMv8.1-PAN implementation to allow specified unprivileged
instructions to execute even when the cpsr.pan bit is set. The
specified instructions generate memory requests with the
TLB::ArmFlags::UserMode flags bit set.

See sections D5.4.2 (About PSTATE.PAN) and G5.6.2 (About the PAN bit)
of the Arm Architecture Reference Manual for details.
https://developer.arm.com/documentation/ddi0487/latest/

Change-Id: I9e904e0154de72c2e4cc70cbc49b3c8407a3cb1d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47779
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-08 08:48:51 +00:00
Giacomo Travaglini
d1cdcb311b misc: Move Mode and Translation from BaseTLB to BaseMMU
This is a step towards moving most of the TLB logic to the
MMU class.

Change-Id: Id6b1fb30aa89960705f165f9738f5b50aa1e6bdb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46779
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-07 08:44:13 +00:00
Giacomo Travaglini
3a72e669dc arch-arm: No need to copy haveLPAE when switching TLBs
When calling the TLB::takeOverFrom, there is no need to
copy the fixed haveLPAE variable as it is a system level
parameter (from ArmSystem) and it is assumed to be the same
for all TLBs (even the switched out)

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I0b010d18ae71e43290f7f76f229c1a231ff42ac0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46899
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-06 12:56:52 +00:00
Daniel R. Carvalho
974a47dfb9 misc: Adopt the gem5 namespace
Apply the gem5 namespace to the codebase.

Some anonymous namespaces could theoretically be removed,
but since this change's main goal was to keep conflicts
at a minimum, it was decided not to modify much the
general shape of the files.

A few missing comments of the form "// namespace X" that
occurred before the newly added "} // namespace gem5"
have been added for consistency.

std out should not be included in the gem5 namespace, so
they weren't.

ProtoMessage has not been included in the gem5 namespace,
since I'm not familiar with how proto works.

Regarding the SystemC files, although they belong to gem5,
they actually perform integration between gem5 and SystemC;
therefore, it deserved its own separate namespace.

Files that are automatically generated have been included
in the gem5 namespace.

The .isa files currently are limited to a single namespace.
This limitation should be later removed to make it easier
to accomodate a better API.

Regarding the files in util, gem5:: was prepended where
suitable. Notice that this patch was tested as much as
possible given that most of these were already not
previously compiling.

Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46323
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-01 19:08:24 +00:00
Giacomo Travaglini
10bb6b076a arch-arm: Remove the TLB::flush overload for TLBI IPA
This will be handled by the MMU

Change-Id: I2cc2cae2a742f3c795867b7b85826e482cacc888
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45782
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-06-10 08:01:01 +00:00
Giacomo Travaglini
af1e8667e1 arch-arm: Remove stage2 TLBI flushes from stage1 flushes
This is not needed anymore as stage2 flush is now handled by
the MMU. With this patch we are progressively removing any link
between stage1 and stage2 TLBs

Change-Id: I3e9e339a78ac972bc536214152f6c68d6a50cb5c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45781
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-10 08:01:01 +00:00
Giacomo Travaglini
a83c2f30df arch-arm: Remove Stage2MMU
The class was adding some complexity on the python/C++ front:

The Stage2MMU was a child of the ArmTLB and parent of the Stage2TLB
However, it's C++ implementation was solely issuing stage2 table walks
and was not handling the stage2 translation logic in general.

We are removing the class and moving its implemetation structures
within the table walker.

This simplifies the code: the nested Stage2Translation class has
been renamed to Stage2Walk to make its purpose more explicit

The MMU has now a centralized view of all TLBs and Table Walkers in the
system

Change-Id: I8a13a5b793abb7e602e9a05a908e7e0ec3c37247
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45780
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-09 18:47:57 +00:00
Daniel R. Carvalho
98ac080ec4 base-stats,misc: Rename Stats namespace as statistics
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Stats became ::statistics.

"statistics" was chosen over "stats" to avoid generating
conflicts with the already existing variables (there are
way too many "stats" in the codebase), which would make
this patch even more disturbing for the users.

Change-Id: If877b12d7dac356f86e3b3d941bf7558a4fd8719
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45421
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
90aab2f926 sim: Rename ProbePoints namespace as probing
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::ProbePoints became ::probing.

"probing" was chosen over "probe_points" because the
namespace contains more than solely probe points; it
contains all classes related to the act of probing.

Change-Id: I44567974a521707593739a2bd5933391803e5b51
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45412
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
e42d2a4789 arch,sim: Rename PseudoInst namespace as pseudo_inst
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::PseudoInst became ::pseudo_inst.

Change-Id: Ie5a8f82a532e5158992ca260b4a24e7c6f311be9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45429
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-26 23:08:21 +00:00
Daniel R. Carvalho
3016478068 base-stats: Rename Units namespace as units
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

Stats::Units became Stats::units.

Change-Id: I9ce855b291db122d952098a090a2984b42152850
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45415
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-26 22:30:33 +00:00
Giacomo Travaglini
da01b59a1c arch-arm: Stop using the DmaPort in the TableWalker
Using a custom TableWalker port instead

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I9e77324569ef0f74f6c8a3941f90bc988abf3c57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45599
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-21 08:32:25 +00:00
Gabe Black
4abe9ac08b misc: Switch away from the deprecated UNIT_* macros.
Expand the macros in place.

Change-Id: I5dba512b99a1204c23a995e112248b86523b77c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45560
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-19 21:42:34 +00:00
Giacomo Travaglini
1cecc752d7 arch-arm: Implement ARMv8.1-VMID16, 16-bit VMID
In an Armv8.1 implementation, when EL2 is using AArch64, the VMID size
is an IMPLEMENTATION DEFINED choice of 8 bits or 16 bits.
When implemented, this feature is supported only when EL2 is using AArch64.
The ID_AA64MMFR1_EL1.VMIDBits field identifies the supported VMID size.

Change-Id: I7acde0a9ba285d4740771133debd60a7a7515954
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45187
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-17 10:22:41 +00:00
Giacomo Travaglini
cf83aec07a arch-arm: Using 16 bit VMID
Change-Id: Ia4f408b8e84b5f52f6b48fd5d4bbc2a5fac87154
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45186
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-17 10:22:41 +00:00
Daniel R. Carvalho
9b675ebea8 misc: Add missing compiler.hh include
Add some missing base/compiler.hh includes.

Found by manually checking the files in:
  grep -r --include \*.hh -L \
    '#include "base/compiler.hh"' \
    $(grep -r -l "GEM5_" src/)

And occasionally checking some .cc files through
a similar methodology.

Change-Id: I6b6e27189c627bb76ace73c338486743d469be46
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45459
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-14 10:02:14 +00:00
Gabe Black
11fe13c311 misc: Replace M5_FALLTHROUGH with GEM5_FALLTHROUGH.
Change-Id: I058f311b6d9c284f745bcc915db72236d05db21b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45233
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-11 20:16:31 +00:00
Gabe Black
fb3befcc6d misc: Replace M5_VAR_USED with GEM5_VAR_USED.
Change-Id: I64a874ccd1a9ac0541dfa01971d7d620a98c9d32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45231
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-05-11 20:16:31 +00:00
Giacomo Travaglini
55498f45dd arch-arm: Move TLB stats update within the lookup method
This is preparing for getTE becoming a MMU method: we still want
those stats to be part of the TLB class as they are TLB related

Change-Id: I7078385fd150144dc5dd4924961e4eaaa7e2446a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35245
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-16 13:12:46 +00:00
Giacomo Travaglini
d1e090eec4 arch-arm: Make TLB misses from a sw prefetch visible
While a TLB hit caused by a prefetching operation is visible in terms
of TLB stats update, this is not the case for a TLB miss, which is
invisible to the stats as it is now.

This patch is realigning the behaviour to be more consistent: we will
always update the stats regardless of whether the access caused a
TLB hit/miss

Change-Id: I161e04fc09a0dbba7468a52848aa7710d1476e19
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37955
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 15:50:22 +00:00
Giacomo Travaglini
c47920d81c arch-arm: Fix atomics permission checks in TLB
For stage 2 translations, atomic accesses were not checking the
access permission bits in the page table descriptors, and were
instead wrongly using the nature of the request itself
(r/w booleans).

Change-Id: I27fbc95f04ea659e77ad5a3afb551873c9c971f0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42073
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-04 09:27:57 +00:00
Hoa Nguyen
9625e90b8e arch-arm,arch-riscv,arch-x86: Add units to stats
Change-Id: I6bf506c223207306d71511491e024546b209030f
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39416
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-02-10 09:03:09 +00:00
Gabe Black
d3a4662a14 arch-arm: Stop "using namespace std"
Change-Id: If0f373bdaadce81c5ebbc37b03810335c42dd10a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39561
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-23 22:48:45 +00:00
Gabe Black
6f74594cc7 arm: Use the "reg" ABI for gem5 ops.
The generic PseudoInstABI just calls back into the ISA specific
getArgument function, and that adds a lot of handling for cases that
aren't used and, besides those, basically just boils down to the "reg"
ABI anyway.

Change-Id: I57e738631dbccbf89cba3a6ca62b1f954b39e959
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39316
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-01-20 21:28:41 +00:00
Giacomo Travaglini
96c0f29b98 arch-arm: Do not use _flushMva for TLBI IPA
This is just a cosmetic change

Change-Id: If9ea1114ed7e20d5c952f401935532cf3335c501
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35246
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-03 09:55:37 +00:00
Giacomo Travaglini
63988cbf7e arch-arm: TlbEntry flush to be considered as functional lookup
Otherwise we are unnecessarily shifting the TLB entry to the
MRU position before invalidating it

Change-Id: I43ee04cd5267829ab7357f4fe1ff745023adc598
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35244
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-03 09:55:11 +00:00
Giacomo Travaglini
e9ee6b1c69 arch-arm: Fix implementation of TLBI_VMALL instructions
Same as 73dfc5f89b81e622a2330b1b52e055cafcc9178b: there's a difference
on how AArch64 and AArch32 treat stage2 invalidation.

Change-Id: I6fede4d9cb82e4bae9163326d38db9351d2a3880
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35243
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-03 09:55:11 +00:00
Giacomo Travaglini
e268bc35a4 arch-arm: Add el2Enabled cached variable
Several TLB invalidation instructions rely on VMID matching.  This is
only applicable is EL2 is implemented and enabled in the current state.

The code prior to this patch was making the now invalid assumption that
we shouldn't consider the VMID if we are doing a secure lookup. This is
because in the past if we were in secure mode we were sure EL2 was not
enabled.
This is fishy and not valid anymore anyway after the introduction of
secure EL2.

Change-Id: I9a1368f8ed19279ed3c4b2da9fcdf0db799bc514
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35242
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-03 09:55:11 +00:00
Gabe Black
d05a0a4ea1 misc: Delete the now unnecessary create methods.
Most create() methods are no longer necessary. This change deletes them,
and occasionally moves some code from them into the constructors they
call.

Change-Id: Icbab29ba280144b892f9b12fac9e29a0839477e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36536
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-30 04:00:20 +00:00
Giacomo Travaglini
ad5fa9ebe4 arch-arm: Fix implementation of TLBI ALLEx instructions
The TLBIALL op in gem5 was designed after the AArch32 TLBIALL instruction.
and was reused by the TLBI ALLEL1, ALLE2, ALLE3 logic.

This is not correct for the following reasons:

- TLBI ALLEx invalidates regardless of the VMID
- TLBI ALLEx (AArch64) is "target regime" oriented, whereas TLBIALL
  (AArch32) is "current regime" oriented

TLBIALL has a different behaviour depending on the current exception
level: if issued at EL1 it will invalidate stage1 translations only; if
at EL2, it will invalidate stage2 translations as well.

TLBI ALLEx is more standard; every TLBI ALLE1 will invalidate stage1 and
stage2 translations. This is because the instruction is not executable
from the guest (EL1)

So for TLBIALL the condition for stage2 forwarding will be:

if (!isStage2 && isHyp) {

Whereas for TLBI ALLEx will be:

if (!isStage2 && target_el == EL1) {

Change-Id: I282f2cfaecbfc883e173770e5d2578b41055bb7a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35241
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-23 16:23:27 +00:00
Giacomo Travaglini
32d88ae46c arch-arm: Rewrite the TLB flushing interface
We are now using an overloaded flush method which has
different TLBI ops as arguments.

This is simplifying the interface and it is allowing us to
encode some state in the TLBIOp which will then be passed
to the TLB. This is a step towards making the TLB a stateless
cache of translations

Change-Id: Ic4fbae72dc3cfe756047148b1cf5f144298c8b08
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35240
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-23 16:23:27 +00:00
Giacomo Travaglini
2a91ea7586 arch-arm: Reimplement TLB::flushAll
flushAll is a non architectural flush command; this is not based on
flushAllSecurity anymore. flushAll should always flush stage1 and stage2,
whereas flushAllSecurity is checking for the current state
(vmid, and if we are in Hyp)

Change-Id: I6b81ebfba387e646f256ecbecb7b5ee720745358
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35239
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-23 16:23:27 +00:00
Gabe Black
91d83cc8a1 misc: Standardize the way create() constructs SimObjects.
The create() method on Params structs usually instantiate SimObjects
using a constructor which takes the Params struct as a parameter
somehow. There has been a lot of needless variation in how that was
done, making it annoying to pass Params down to base classes. Some of
the different forms were:

const Params &
Params &
Params *
const Params *
Params const*

This change goes through and fixes up every constructor and every
create() method to use the const Params & form. We use a reference
because the Params struct should never be null. We use const because
neither the create method nor the consuming object should modify the
record of the parameters as they came in from the config. That would
make consuming them not idempotent, and make it impossible to tell what
the actual simulation configuration was since it would change from any
user visible form (config script, config.ini, dot pdf output).

Change-Id: I77453cba52fdcfd5f4eec92dfb0bddb5a9945f31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35938
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-14 12:06:44 +00:00
Jordi Vaquero
05e60080dc arch-arm: Implement Armv8.2-LPA
This is enabled by setting the ArmSystem.phys_addr_range64 to 52.
This will automatically set the ID_AA64MMFR0_EL1.PARange to 0b0110
which encodes the presence of Armv8.2-LPA

Change-Id: If9b36e26cd2a72e55c8e929a632b7b50d909b282
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35956
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-14 06:56:47 +00:00
Gabe Black
b877efa6d4 misc: Update attribute syntax, and reorganize compiler.hh.
This change replaces the __attribute__ syntax with the now standard [[]]
syntax. It also reorganizes compiler.hh so that all special macros have
some explanatory text saying what they do, and each attribute which has a
standard version can use that if available and what version of c++ it's
standard in is put in a comment.

Also, the requirements as far as where you put [[]] style attributes are
a little more strict than the old school __attribute__ style. The use of
the attribute macros was updated to fit these new, more strict
requirements.

Change-Id: Iace44306a534111f1c38b9856dc9e88cd9b49d2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35219
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-09-28 21:52:59 +00:00
Shivani Parekh
392c1ced53 misc: Replaced master/slave terminology
Change-Id: I4df2557c71e38cc4e3a485b0e590e85eb45de8b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33553
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-09-10 23:02:28 +00:00
Emily Brickey
a65eed883b arch-arm: convert tlb to new style stats
Change-Id: I2a3f138b53496be6361a1a2b81fa471a56a4dc10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32794
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-08-18 16:35:02 +00:00