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arch-arm: Using 16 bit VMID

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Change-Id: Ia4f408b8e84b5f52f6b48fd5d4bbc2a5fac87154
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45186
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-12-04 16:55:01 +00:00
parent 26c03495fa
commit cf83aec07a
6 changed files with 15 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/arch/arm/pagetable.hh
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@@ -44,6 +44,7 @@
#include <cstdint>
#include "arch/arm/page_size.hh"
#include "arch/arm/types.hh"
#include "arch/arm/utility.hh"
#include "sim/serialize.hh"
@@ -109,7 +110,7 @@ struct TlbEntry : public Serializable
// use (AArch32 w/ LPAE and AArch64)
uint16_t asid; // Address Space Identifier
uint8_t vmid; // Virtual machine Identifier
vmid_t vmid; // Virtual machine Identifier
uint8_t N; // Number of bits in pagesize
uint8_t innerAttrs;
uint8_t outerAttrs;
@@ -188,22 +189,22 @@ struct TlbEntry : public Serializable
}
bool
match(Addr va, uint8_t _vmid, bool hypLookUp, bool secure_lookup,
match(Addr va, vmid_t _vmid, bool hyp_lookup, bool secure_lookup,
ExceptionLevel target_el, bool in_host) const
{
return match(va, 0, _vmid, hypLookUp, secure_lookup, true,
return match(va, 0, _vmid, hyp_lookup, secure_lookup, true,
target_el, in_host);
}
bool
match(Addr va, uint16_t asn, uint8_t _vmid, bool hypLookUp,
match(Addr va, uint16_t asn, vmid_t _vmid, bool hyp_lookup,
bool secure_lookup, bool ignore_asn, ExceptionLevel target_el,
bool in_host) const
{
bool match = false;
Addr v = vpn << N;
if (valid && va >= v && va <= v + size && (secure_lookup == !nstid) &&
(hypLookUp == isHyp))
(hyp_lookup == isHyp))
{
match = checkELMatch(target_el, in_host);

2
src/arch/arm/table_walker.cc
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@@ -189,7 +189,7 @@ TableWalker::drainResume()
Fault
TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid,
uint8_t _vmid, bool _isHyp, TLB::Mode _mode,
vmid_t _vmid, bool _isHyp, TLB::Mode _mode,
TLB::Translation *_trans, bool _timing, bool _functional,
bool secure, TLB::ArmTranslationType tranType,
bool _stage2Req)

5
src/arch/arm/table_walker.hh
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@@ -44,6 +44,7 @@
#include "arch/arm/regs/misc.hh"
#include "arch/arm/system.hh"
#include "arch/arm/tlb.hh"
#include "arch/arm/types.hh"
#include "mem/request.hh"
#include "params/ArmTableWalker.hh"
#include "sim/clocked_object.hh"
@@ -744,7 +745,7 @@ class TableWalker : public ClockedObject
/** ASID that we're servicing the request under */
uint16_t asid;
uint8_t vmid;
vmid_t vmid;
bool isHyp;
/** Translation state for delayed requests */
@@ -941,7 +942,7 @@ class TableWalker : public ClockedObject
PortID idx=InvalidPortID) override;
Fault walk(const RequestPtr &req, ThreadContext *tc,
uint16_t asid, uint8_t _vmid,
uint16_t asid, vmid_t _vmid,
bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
bool timing, bool functional, bool secure,
TLB::ArmTranslationType tranType, bool _stage2Req);

2
src/arch/arm/tlb.cc
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@@ -164,7 +164,7 @@ TLB::finalizePhysical(const RequestPtr &req,
}
TlbEntry*
TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure,
TLB::lookup(Addr va, uint16_t asn, vmid_t vmid, bool hyp, bool secure,
bool functional, bool ignore_asn, ExceptionLevel target_el,
bool in_host, BaseTLB::Mode mode)
{

4
src/arch/arm/tlb.hh
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@@ -222,7 +222,7 @@ class TLB : public BaseTLB
* @param mode to differentiate between read/writes/fetches.
* @return pointer to TLB entry if it exists
*/
TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
TlbEntry *lookup(Addr vpn, uint16_t asn, vmid_t vmid, bool hyp,
bool secure, bool functional,
bool ignore_asn, ExceptionLevel target_el,
bool in_host, BaseTLB::Mode mode);
@@ -423,7 +423,7 @@ protected:
bool isHyp;
TTBCR ttbcr;
uint16_t asid;
uint8_t vmid;
vmid_t vmid;
PRRR prrr;
NMRR nmrr;
HCR hcr;

2
src/arch/arm/types.hh
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@@ -51,6 +51,8 @@ namespace ArmISA
{
typedef uint32_t MachInst;
typedef uint16_t vmid_t;
BitUnion8(ITSTATE)
/* Note that the split (cond, mask) below is not as in ARM ARM.
* But it is more convenient for simulation. The condition