From cf83aec07a039652eccc7a7b12493f1d68bc1a29 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 4 Dec 2019 16:55:01 +0000 Subject: [PATCH] arch-arm: Using 16 bit VMID Change-Id: Ia4f408b8e84b5f52f6b48fd5d4bbc2a5fac87154 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45186 Reviewed-by: Richard Cooper Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- src/arch/arm/pagetable.hh | 11 ++++++----- src/arch/arm/table_walker.cc | 2 +- src/arch/arm/table_walker.hh | 5 +++-- src/arch/arm/tlb.cc | 2 +- src/arch/arm/tlb.hh | 4 ++-- src/arch/arm/types.hh | 2 ++ 6 files changed, 15 insertions(+), 11 deletions(-) diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh index a8c3a142b9..35053b2f48 100644 --- a/src/arch/arm/pagetable.hh +++ b/src/arch/arm/pagetable.hh @@ -44,6 +44,7 @@ #include #include "arch/arm/page_size.hh" +#include "arch/arm/types.hh" #include "arch/arm/utility.hh" #include "sim/serialize.hh" @@ -109,7 +110,7 @@ struct TlbEntry : public Serializable // use (AArch32 w/ LPAE and AArch64) uint16_t asid; // Address Space Identifier - uint8_t vmid; // Virtual machine Identifier + vmid_t vmid; // Virtual machine Identifier uint8_t N; // Number of bits in pagesize uint8_t innerAttrs; uint8_t outerAttrs; @@ -188,22 +189,22 @@ struct TlbEntry : public Serializable } bool - match(Addr va, uint8_t _vmid, bool hypLookUp, bool secure_lookup, + match(Addr va, vmid_t _vmid, bool hyp_lookup, bool secure_lookup, ExceptionLevel target_el, bool in_host) const { - return match(va, 0, _vmid, hypLookUp, secure_lookup, true, + return match(va, 0, _vmid, hyp_lookup, secure_lookup, true, target_el, in_host); } bool - match(Addr va, uint16_t asn, uint8_t _vmid, bool hypLookUp, + match(Addr va, uint16_t asn, vmid_t _vmid, bool hyp_lookup, bool secure_lookup, bool ignore_asn, ExceptionLevel target_el, bool in_host) const { bool match = false; Addr v = vpn << N; if (valid && va >= v && va <= v + size && (secure_lookup == !nstid) && - (hypLookUp == isHyp)) + (hyp_lookup == isHyp)) { match = checkELMatch(target_el, in_host); diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 1b36f93a50..7218e15fb3 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -189,7 +189,7 @@ TableWalker::drainResume() Fault TableWalker::walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid, - uint8_t _vmid, bool _isHyp, TLB::Mode _mode, + vmid_t _vmid, bool _isHyp, TLB::Mode _mode, TLB::Translation *_trans, bool _timing, bool _functional, bool secure, TLB::ArmTranslationType tranType, bool _stage2Req) diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index 4f0373a48e..778874782b 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -44,6 +44,7 @@ #include "arch/arm/regs/misc.hh" #include "arch/arm/system.hh" #include "arch/arm/tlb.hh" +#include "arch/arm/types.hh" #include "mem/request.hh" #include "params/ArmTableWalker.hh" #include "sim/clocked_object.hh" @@ -744,7 +745,7 @@ class TableWalker : public ClockedObject /** ASID that we're servicing the request under */ uint16_t asid; - uint8_t vmid; + vmid_t vmid; bool isHyp; /** Translation state for delayed requests */ @@ -941,7 +942,7 @@ class TableWalker : public ClockedObject PortID idx=InvalidPortID) override; Fault walk(const RequestPtr &req, ThreadContext *tc, - uint16_t asid, uint8_t _vmid, + uint16_t asid, vmid_t _vmid, bool _isHyp, TLB::Mode mode, TLB::Translation *_trans, bool timing, bool functional, bool secure, TLB::ArmTranslationType tranType, bool _stage2Req); diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index bf6d0bb044..c367d47acf 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -164,7 +164,7 @@ TLB::finalizePhysical(const RequestPtr &req, } TlbEntry* -TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure, +TLB::lookup(Addr va, uint16_t asn, vmid_t vmid, bool hyp, bool secure, bool functional, bool ignore_asn, ExceptionLevel target_el, bool in_host, BaseTLB::Mode mode) { diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 5aa72b5ebf..3d531b760e 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -222,7 +222,7 @@ class TLB : public BaseTLB * @param mode to differentiate between read/writes/fetches. * @return pointer to TLB entry if it exists */ - TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, + TlbEntry *lookup(Addr vpn, uint16_t asn, vmid_t vmid, bool hyp, bool secure, bool functional, bool ignore_asn, ExceptionLevel target_el, bool in_host, BaseTLB::Mode mode); @@ -423,7 +423,7 @@ protected: bool isHyp; TTBCR ttbcr; uint16_t asid; - uint8_t vmid; + vmid_t vmid; PRRR prrr; NMRR nmrr; HCR hcr; diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index c3e8db93b0..2ec5255add 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -51,6 +51,8 @@ namespace ArmISA { typedef uint32_t MachInst; + typedef uint16_t vmid_t; + BitUnion8(ITSTATE) /* Note that the split (cond, mask) below is not as in ARM ARM. * But it is more convenient for simulation. The condition