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arch-arm: Implement ARMv8.1-VMID16, 16-bit VMID

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In an Armv8.1 implementation, when EL2 is using AArch64, the VMID size
is an IMPLEMENTATION DEFINED choice of 8 bits or 16 bits.
When implemented, this feature is supported only when EL2 is using AArch64.
The ID_AA64MMFR1_EL1.VMIDBits field identifies the supported VMID size.

Change-Id: I7acde0a9ba285d4740771133debd60a7a7515954
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45187
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-12-04 16:58:16 +00:00
parent cf83aec07a
commit 1cecc752d7
4 changed files with 39 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/arch/arm/isa.cc
View File

@@ -2177,6 +2177,7 @@ ISA::setMiscReg(int misc_reg, RegVal val)
case MISCREG_TCR_EL1:
case MISCREG_TCR_EL2:
case MISCREG_TCR_EL3:
case MISCREG_VTCR_EL2:
case MISCREG_SCTLR_EL2:
case MISCREG_SCTLR_EL3:
case MISCREG_HSCTLR:

3
src/arch/arm/regs/misc_types.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2020 ARM Limited
* Copyright (c) 2010-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -563,6 +563,7 @@ namespace ArmISA
Bitfield<13, 12> sh0;
Bitfield<15, 14> tg0;
Bitfield<18, 16> ps; // Only defined for VTCR_EL2
Bitfield<19> vs; // Only defined for VTCR_EL2
Bitfield<21> ha; // Only defined for VTCR_EL2
Bitfield<22> hd; // Only defined for VTCR_EL2
EndBitUnion(VTCR_t)

33
src/arch/arm/tlb.cc
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2013, 2016-2020 ARM Limited
* Copyright (c) 2010-2013, 2016-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1373,6 +1373,35 @@ TLB::getTableWalkerPort()
return &stage2Mmu->getDMAPort();
}
vmid_t
TLB::getVMID(ThreadContext *tc) const
{
AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
VTCR_t vtcr = tc->readMiscReg(MISCREG_VTCR_EL2);
vmid_t vmid = 0;
switch (mmfr1.vmidbits) {
case 0b0000:
// 8 bits
vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48);
break;
case 0b0010:
if (vtcr.vs && ELIs64(tc, EL2)) {
// 16 bits
vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 63, 48);
} else {
// 8 bits
vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48);
}
break;
default:
panic("Reserved ID_AA64MMFR1_EL1.VMIDBits value: %#x",
mmfr1.vmidbits);
}
return vmid;
}
void
TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
{
@@ -1457,7 +1486,7 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
scr = tc->readMiscReg(MISCREG_SCR_EL3);
isPriv = aarch64EL != EL0;
if (haveVirtualization) {
vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48);
vmid = getVMID(tc);
isHyp = aarch64EL == EL2;
isHyp |= tranType & HypMode;
isHyp &= (tranType & S1S2NsTran) == 0;

6
src/arch/arm/tlb.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2013, 2016, 2019-2020 ARM Limited
* Copyright (c) 2010-2013, 2016, 2019-2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -443,6 +443,10 @@ protected:
void updateMiscReg(ThreadContext *tc,
ArmTranslationType tranType = NormalTran);
/** Returns the current VMID
* (information stored in the VTTBR_EL2 register) */
vmid_t getVMID(ThreadContext *tc) const;
public:
void invalidateMiscReg() { miscRegValid = false; }