Commit Graph

16365 Commits

Author SHA1 Message Date
Nikos Nikoleris
f06dcf9d1f util: Relax commit message checker to allow fixups
Change-Id: I094de0a9cb65af0ba0a8700d77cd51c6537d7beb
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37598
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-11-20 16:32:02 +00:00
Matthew Poremba
ce06a4715e util: Use MAINTAINERS.yaml for valid tags in git hook
There is a mismatch between the tags in MAINTAINERS.yaml and the
valid_tags in the git hook. This means if a user consults the
MAINTAINERS.yaml file to find the appropriate tag, there is a chance of
the commit being rejected due to this mismatch. Now that the maintainers
file is in yaml format, use the util/maint library to parse the valid
tag options. Additional meta tags are added (WIP, RFC) and tags that
were previously valid but not in the MAINTAINERS.yaml file.

Change-Id: I3de8f0b6f8507aa1afd2118bc4373ac0610cce40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37220
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-20 16:32:02 +00:00
Hoa Nguyen
ed3e52663b mem-ruby,misc: Fix a parameter name in a DeprecatedParam message
Change-Id: Ie84a29e779187effea372c6289688f32a1db075d
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36635
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-20 13:52:51 +00:00
Giacomo Travaglini
692128dd32 python: Fix toBool converter
It was using an undefined variable (result) which was mistakenly left
there after its latest refactor

Change-Id: I50bb9b1e7793045556a29306faea5f455b29819d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37755
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-20 11:24:12 +00:00
Hoa Nguyen
e175be98fb sim,stats: Update stats style for power_model and thermal_domain
Change-Id: Ie50553c301ff5790b51057dc117568374f0cbe36
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36515
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2020-11-20 06:05:14 +00:00
Hoa Nguyen
836920ac5d mem,stats: Update stats style for mem/probes and mem/qos
Change-Id: I47a094eb8fc56ef998ec3c971dab68ba39b092e3
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36476
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 22:46:48 +00:00
Hoa Nguyen
83ad47415d mem,stats: Update stats style for FALRU
Change-Id: I67a202eb974a31851fbbce0f15b5377ba726bc1c
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36475
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 22:46:48 +00:00
Hoa Nguyen
856d66d9ba dev,stats: Update stats style for CopyEngine and IdeDisk
Change-Id: Ib757b00864bc144b20adef974e3443ddba2945f0
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36436
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 22:46:48 +00:00
Hoa Nguyen
3db48cbbc6 dev,stats: Update stats style of src/dev/net
Change-Id: I06c41a0506415c7a4f2608668b90d328c2789e61
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36435
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 22:46:48 +00:00
Hoa Nguyen
159cc734eb dev-arm,stats: Update stats style of src/dev/arm
Change-Id: I722e88801bb8ca0f0d75b5a1bf271fa4d4eded17
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36415
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 22:46:48 +00:00
Hoa Nguyen
81c2978e6c cpu,stats: Update stats style for base.hh and base.cc
Change-Id: Ib34dcb294370ea66e3526ab35660d8b50668bebe
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36297
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 22:46:48 +00:00
Hoa Nguyen
2771d1ae1e cpu-simple,stats: Update stats style
Change-Id: I1e9c7c464f1f7b4b354e9a47c7d974c6806b45da
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36295
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 22:46:48 +00:00
Hoa Nguyen
84fa2b46d9 cpu-o3,stats: Update stats style for mem_dep_unit.hh
Change-Id: I9bd8e9bc331f5d57c1b6320a87b14e9b94465148
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36215
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 22:46:48 +00:00
Hoa Nguyen
765ba547a2 cpu-o3,stats: Update stats style for cpu.hh and cpu.cc
Change-Id: If4ddaf6a9a84ea71fa19f5ca6d2e5294ec9a0b23
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36195
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 22:46:48 +00:00
Hoa Nguyen
d9673c88d7 cpu-o3,stats: Update stats style of inst_queue & inst_queue_impl
Change-Id: I95c2e194e757437fb8c3b3f530bce363e24f9a8e
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36176
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 22:46:48 +00:00
Hoa Nguyen
13176f9fd0 cpu-o3,stats: Update stats style for iew and iew_impl
Change-Id: Ie213aeb402fee5f015f10c9c03e5b9c02ba1f3fe
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36095
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 22:46:48 +00:00
Hoa Nguyen
a71f3e1a29 cpu-minor,stats: Update stats style of MinorCPU
Change-Id: Id14e6816cc82603459bf68461ae40bf2b63080eb
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36075
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 22:46:48 +00:00
Giacomo Travaglini
c35a237b12 fastmodel: Replace xrange with range to be python3 compliant
Change-Id: I69ef5d744e2642af95383fbda920464178380757
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37716
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 17:20:32 +00:00
Giacomo Travaglini
1569f5e5cd fastmodel: Use BaseMMU in the CortexR52 wrapper
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I569dc66a9dad54a374b0864ef2ffabd114aede7b
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37715
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 17:20:32 +00:00
Jui-min Lee
fc44c22d2d systemc: Make tlm/gem5 packet conversion flexible
We used to have a hard-coded packet2payload and payload2packet in the
tlm_bridge implementation. However, as the conversion is operated on
generic tlm payload, we're not able to handle information stored in any
user defined SystemC extensions.

In this CL, we add a pair of function to register extra conversion steps
between tlm payload and gem5 packet. This decouples the exact conversion
logic and enables SystemC users to register any necessary steps for
their extensions.

Change-Id: I70b3405395fed0f757f0fb7e19136f47d84ac115
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37075
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 07:50:20 +00:00
Gabe Black
995e1d2331 arch: Add some format strings to the parser for reg indexes.
There are two new strings, reg_idx_arr_decl which declares the source
and dest register index arrays, and set_reg_idx_arr which installs them
in the base class.

The set_reg_idx_arr code needs to implicitly figure out what type to use
based on the type of the "this" pointer. The name of the containing
class is not *necessarily* the same as class_name, since the generated
code can use that name, something based on that name, or whatever else
it wants. No other format string (other than class_name itself) uses the
class name internally, so we can't count on that working in existing ISA
definitions.

Change-Id: Id995a46896e71a2fcf3103c34a1e1e67e24f88f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36878
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 02:52:05 +00:00
Gabe Black
5e61828571 cpu: Add an StaticInst accessor for setting register index storage.
Change-Id: I66adccd8851f035b5d61ace9153ae7acc57403ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36877
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 02:51:29 +00:00
Xiongfei
088c8a224c cpu-minor: this is a bug fix for MinorCPU for thread cloning.
Inside the code of cloneFunc(…)  //syscall_emul.hh

    cp->initState();  //line 1483
    p->clone(tc, ctc, cp, flags);  //line 1484
    …
    ctc->clearArchRegs(); //line 1503

    OS::archClone(flags, p, cp, tc, ctc, newStack, tlsPtr); //line 1505
    …

At line 1483, initState() is called and the activateContext() of the
corresponding MinorCPU is eventually called. The actual architecture
clone happens at line 1505 where PC of the new thread could have a
correct value.

In the existing implementation of MinorCPU::activateContext(ThreadID
thread_id), the below line 275 is called
    pipeline->wakeupFetch(thread_id);
to start fetching instruction with current value of PC, which is 0x0,
leading to panic “Page table fault when accessing virtual address 0”.

This is because the OS::archClone() is not yet called. So, the below bug
fix handles the wakeup fetch for a thread for two scenarios:
   ...
    if (!threads[thread_id]->getUseForClone())
    { //the thread is not cloned
        pipeline->wakeupFetch(thread_id);
    } else {//the thread from clone
        if (fetchEventWrapper != NULL)
            delete fetchEventWrapper;
        fetchEventWrapper = new EventFunctionWrapper([this, thread_id]
          {pipeline->wakeupFetch(thread_id);}, "wakeupFetch");
        schedule(*fetchEventWrapper, clockEdge(Cycles(0)));
    }
    ...
If a thread is not cloned, pipeline->wakeupFetch() is called
immediately.
For the cloned thread, the above bug fix delays the execution of
    pipeline->wakeupFetch()
after the OS::archClone is done. ThreadContext::getUseForClone() return
true if a thread is cloned.

A member variable fetchEventWrapper is added to MinorCPU class for
delayed fetch event.

A member variable useForClone and its corresponding get/set methods are
added to ThreadContext class. This approach allows future reuse of this
useForClone variable by other CPU models if needed and also avoid lots
of changes resulted by modifying parameters of activateContext () and
activate() which are defined as override.

Inside the syscall cloneFunc, the useForClone member of a ThreadContext
object is set via its set method right before Process's initState() is
called, shown as below.
    ctc->setUseForClone(true);
    cp->initState();
    p->clone(tc, ctc, cp, flags);

A few previously failed RISC-V ASM tests have been open in tests.py file
after the bug fix works.

JIRA issue: https://gem5.atlassian.net/browse/GEM5-374

Change-Id: Ibffe46522e2617443d29f49df180692c54830f14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37315
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 02:47:48 +00:00
Gabe Black
7039662eeb x86: Fix object scope in the CPUID code.
The original version of the code takes a pointer from a temporary object
which gets destroyed before the pointer is used.

Change-Id: I16af4eefdf202f769a672e230330d8e0bfce3bb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37695
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-19 01:40:30 +00:00
Bobby R. Bruce
710ff0e99d arch-gcn3,misc: Added missing overrides to gpu_thread.hh
Compiling GCN3 with clang will result in errors within this change.

Change-Id: I05fea6f84f988cb22505281fa24e72d615959f7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37538
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
2020-11-18 18:50:11 +00:00
Gabe Black
9fc5344c0a cpu: Access src and dest reg indexes using a pointer to member.
This will eventually let subclasses provide their own appropriately
sized storage for these indexes. By using a pointer to member instead of
a regular pointer, we ensure that even if the StaticInst is copied/moved
somewhere, it will still find its indexes correctly, without any
additional performance overhead or maintenance.

Unfortunately C++ has decided that arrays with known bounds are not
convertible/compatible with arrays with unknown bounds. I've found at
least two standards proposals in various stages of acceptance which say
that that's dumb and they should change that (because it's dumb and they
should change that), but in the mean time we can get everything to
compile by using the reinterpret_cast hammer. While this is
*technically* undefined behavior, it's basically not and should be
pretty safe.

Change-Id: Id747b0cf68d1a0b4809ebb66a32472187110d7d8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36876
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2020-11-18 11:52:24 +00:00
Bobby R. Bruce
95a8cf76a5 arch-gcn3, misc: Added missing override to protocol_tester.hh
Clang will return a missing-override error when compiling X86_GCN4
without this change.

Change-Id: Ib5fd9ba5c27ddc15561198bfc90d27b7599a7923
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37537
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 22:46:40 +00:00
Bobby R. Bruce
a1ac9df60a arch-sparc,misc: Added M5_VAR_USED to SparcProcess var
Compiling sparc/gem5.fast fails without specifying this variable is
used.

Change-Id: I86aa5c6495de111421458c2b62200ddb2a89076e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37536
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 22:46:40 +00:00
Bobby R. Bruce
20456a4d34 mem-cache,misc: Added missing override to operator
Clang compilation was failing in error due to this missing override.

Change-Id: I92f1774cd2f1f5ef90ab1d72d038f6c65cba70ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37535
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 22:46:40 +00:00
Gabe Black
7811d01f07 dev: Delete the unused DLAB member in the 8250 UART.
This value is never actually used. The value is computed from the LCR
each time it's needed instead.

Change-Id: I6dc5580eb03174f32b8a381cd2974f742b8eb472
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36817
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 22:26:06 +00:00
Gabe Black
07c234f0f3 dev: Convert the IDE controller to use the RegisterBank types.
Also get rid of the "ideConfig" register which does not actually show up
in the spec corresponding to this device's PCI IDs.

Change-Id: Id5d109403f49d956c696371b4d93d26150cc96dc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36816
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 22:25:56 +00:00
Kyle Roarty
9e1f543407 arch-gcn3: Explicitly sign-extend simm16
In some instructions, simm16 needs to be sign extended. Previous code
simply casted the simm16 to a 32-bit or 64-bit datatype, however this
didn't actually sign-extend the value.

This patch explicitly calls sext<16> on simm16 whenever it's supposed
to be sign-extended.

Change-Id: I32f02e51fbab220d1a73dc7e68c7410937db21c7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37495
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 17:08:24 +00:00
Kyle Roarty
a107f62b41 mem-ruby: Fix deadlock in VIPERCoalescer
Certain instructions (some atomics and buffer_wbinvl1_vol) deadlock
in the coalescer, where sendTimingReq fails, fails a retry, and then
never retries again.

This fix sets m_cache_inv_pkt to null before calling
completeHitCallback(), as that allows the failed packets to be retried
again.

Change-Id: I4a51c741360f385f8b4c3f2a31a9410f18e095d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37477
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 17:08:24 +00:00
Kyle Roarty
5f6ebe752e arch-gcn3: Implement flat_load_sbyte instruction
Change-Id: I3aa7547a393b9ecb4b3d4d107394c54d690a0ac2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37476
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 17:08:24 +00:00
Kyle Roarty
c1ddd01b66 arch-gcn3: Implement s_setreg_imm32_b32 instruction
Change-Id: I5383243403156dc17d4997106085a62fb0483fec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37475
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 17:08:24 +00:00
Jordi Vaquero
b0dbc09b3f arch-arm: Implementation ARMv8.1 RDMA
Adding RDMA implementation for ARMv8.1
    + isa/formats/*: Adding decoding of Aarch64 and aarch32 instructions
    + isa/insts/neon.isa\neon64.isa: Adding function instructions

Change-Id: I430e8880723f373ffffa50079a87fd4ecc634d86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36015
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 11:45:35 +00:00
Isaac Sánchez Barrera
caf6a507cb base: Prevent undefined behavior in not interleaved AddrRanges.
If an `AddrRange` is not interleaved, return the input address in
`removeIntlvBits` and `addIntlvBits` to prevent undefined behavior.  It
allows to use these methods in all cases without having to check
manually whether the range is interleaved.

Change-Id: Ic6ac8c4e52b09417bc41aa9380a24319c34e0b35
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37617
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-11-17 10:46:30 +00:00
Gabe Black
2f8b5acba1 fastmodel: Wrap the PL330 DMA controller fast model.
Change-Id: I0290e52ede4dca1252ca224abcc85c2c8086ea3c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37216
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-17 06:48:13 +00:00
Daniel Gerzhoy
9a01d3e927 dev-hsa,gpu-compute: Agent Packet handler implemented.
HSA packet processor will now accept and process agent packets.

Type field in packet is command type.
For now:
        AgentCmd::Nop = 0
        AgentCmd::Steal = 1

Steal command steals the completion signal for a running kernel.
This enables a benchmark to use hsa primitives to send an agent
packet to steal the signal, then wait on that signal.

Minimal working example to be added in gem5-resources.

Change-Id: I37f8a4b7ea1780b471559aecbf4af1050353b0b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37015
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-16 16:12:48 +00:00
Ciro Santilli
a0cff8b945 arch-arm: move serialize and unserialize definition to cpp file
Change-Id: I9ac64184d3fe36617f474a714b228b55b9a90976
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36115
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-16 09:16:14 +00:00
Daniel R. Carvalho
833a60a7aa base,cpu,mem: Use templatized SatCounter
Change the deprecated SatCounter instances to the new type-size-
aware SatCounters.

Jira: https://gem5.atlassian.net/browse/GEM5-813

Change-Id: Ie943c553dd8a8c24c80e737783708b033ce001da
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37095
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2020-11-14 10:01:43 +00:00
Daniel R. Carvalho
37add2103c base: Templatize SatCounter
Allow SatCounter to have larger unsigned types to accomodate
larger counters.

The template decision was taken because some predictors will
generate huge arrays of small counters, so smaller types will
lessen their overhead; however, isolated counters may require
any counter size.

Jira: https://gem5.atlassian.net/browse/GEM5-813

Change-Id: I5475a565ea7b97d1dfc176fa9d7cf827560fbe39
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37135
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-14 10:01:43 +00:00
Gabe Black
8e34e0b920 scons: Add support for GRPC protobuf files.
These files are used to generate stubs for calling across GRPC
protocols, an RPC mechanism which is based around the protocol buffer
system.

The support for these files is heavily based on and calls into the
existing protobuf file support, but with the extra step which generates
the additional .grpc.pb.cc and .grpc.pb.h files.

Change-Id: I89022928c08aa9f7ed024b7380ddcc54ca75b55e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37277
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 22:08:42 +00:00
Gabe Black
6bbdfa370c scons: Convert ProtoBuf to use a scons Builder and Scanner.
There are several benefits to using a Builder. First, the action we're
executing is shared between all uses of the Builder. The number of
times this particular builder is called is small, but it should still
be a little more efficient.

Second, we can use SCons's emitter mechanism to generate the .pb.cc and
.pb.h target files in a little more general way.

Also, this change adds a Scanner for .proto files which will scan them
for imports and let SCons manage those implicit dependencies properly.
The scanner is a bit simplistic as described in a comment in the
source, but should work pretty well in practice with reasonably
formatted files, and in particular some files I'm working with that
include imports.

Change-Id: Iaf2498e61133d6f713d6ccaf199422b882c5894f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37276
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 22:08:21 +00:00
Gabe Black
0957ab118c scons: Consolidate the ProtoBuf code.
The ProtoBuf support in src/SConscript was split into two parts, one
where the ProtoBuf sources were declared, and the other where scons was
told how to buld the .cc and .hh files and the .cc was added to the
build.

As far as I can tell, there was no real reason to have things split up
like that, at least not currently. This change moves everything into
the ProtoBuf class definition, and this should behave the same as
before but be a little easier to understand and maintain.

Change-Id: I02320f50ece53d90c14b5062bd6b1167210f46c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37275
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 22:08:02 +00:00
Gabe Black
598f15cf24 scons: Fix how directories are handled for protobuf files.
There were two issues with how paths were handled for these files.

1. The code in the ProtoBuf class would drop the subdirectory part of
the path name when generating the name of the .cc and .h files the
protoc compiler would output. Since protoc wouldn't generate files
where scons expected, it would fail when it tried to build the .cc.

2. protoc will use the --proto_path and --cpp_out settings to figure
out what path to use for generated files. It will remove the
--proto_path prefix it found the .proto file with from the files path,
and then add the rest to the --cpp_out prefix.

The input files should come from the build directory using symlinks
set up by scons, and the output files should end up alongside them.
That means the --proto_path setting should be the build directory, and
so should --cpp_out. That's fortunately simpler than what was there
before, since it doesn't depend on what the source or targets are.

Change-Id: I69692d2fe3813011982f0c1c9824589a132f93ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37218
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 22:07:42 +00:00
Gabe Black
760e18e35b mem-cache: Remove "inline" from a method in one of the prefetchers.
The function was defined in a .cc file but marked as inline. gcc seems
to often figure out what it should do, but in clang it doesn't export
the function (since it's marked as inline), and during linking external
references, which don't have a local copy since it's not defined in the
.hh file, will fail.

This failure looks particularly odd because the funciton is virtual,
and so the failure is reported as being unable to compose the vtable
in places where the object is constructed, relatively obscure code
which is generated by the build system and obscured by templates from
an external code base (pybind11).

Change-Id: Ib51aefbf9005e4ca8dfebef32c5def472175f115
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37436
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 22:04:42 +00:00
Daniel R. Carvalho
97a766100b mem-cache: Override print function of sector and super blocks
Pass management of printing sector and super block's contents to them.

Change-Id: Ided8d404450a0fa39127ac7d2d6578d95691f509
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36582
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 21:46:43 +00:00
Daniel R. Carvalho
c8f3ff5e18 mem-cache: Use the compression factor to co-allocate
The compression factor of a block is measured according to the maximum
achievable compression ratio.

For example, if up to 4 blocks can co-allocate in a superblock, and
a cache line has 512 bits, the possible compression factors are 1
(uncompressed, <=512 bits), 2 (compressed, <=256 bits), 4 (compressed,
<=128 bits).

This is an approach similar to the one described in "Yet Another
Compressed Cache", by Sardashti et al.

Change-Id: I52ef36989f3eeef6fc8890132a57f995ef9c5258
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36581
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 21:46:43 +00:00
Daniel R. Carvalho
90de6ec221 mem-cache: Set compression bit with its size
When setting the size of a compressed block, its compressibility
needs to be recalculated based on that, so move such functionality
to be done after the block has been inserted, within setSizeBits.

As a side effect, insertBlock does not need to be overridden
anymore.

Change-Id: I608f876cd2110ac5e394ffad5b29941ba458ba91
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36580
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-11-12 21:46:43 +00:00