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arch-arm: move serialize and unserialize definition to cpp file

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Change-Id: I9ac64184d3fe36617f474a714b228b55b9a90976
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36115
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Ciro Santilli
2020-10-15 10:04:05 +01:00
parent 833a60a7aa
commit a0cff8b945
2 changed files with 18 additions and 15 deletions
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16
src/arch/arm/isa.cc
View File

@@ -2350,6 +2350,22 @@ ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)
}
}
void
ISA::serialize(CheckpointOut &cp) const
{
DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
}
void
ISA::unserialize(CheckpointIn &cp)
{
DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
updateRegMap(tmp_cpsr);
}
void
ISA::addressTranslation64(TLB::ArmTranslationType tran_type,
BaseTLB::Mode mode, Request::Flags flags, RegVal val)

17
src/arch/arm/isa.hh
View File

@@ -810,21 +810,8 @@ namespace ArmISA
static void zeroSveVecRegUpperPart(VecRegContainer &vc,
unsigned eCount);
void
serialize(CheckpointOut &cp) const override
{
DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
}
void
unserialize(CheckpointIn &cp) override
{
DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
updateRegMap(tmp_cpsr);
}
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
void startup() override;