diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 217f432ac7..9b1cde31f5 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2350,6 +2350,22 @@ ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount)
     }
 }
 
+void
+ISA::serialize(CheckpointOut &cp) const
+{
+    DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
+    SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+}
+
+void
+ISA::unserialize(CheckpointIn &cp)
+{
+    DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
+    UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+    CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
+    updateRegMap(tmp_cpsr);
+}
+
 void
 ISA::addressTranslation64(TLB::ArmTranslationType tran_type,
     BaseTLB::Mode mode, Request::Flags flags, RegVal val)
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 4a824edce8..6b9dd3c70e 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -810,21 +810,8 @@ namespace ArmISA
         static void zeroSveVecRegUpperPart(VecRegContainer &vc,
                                            unsigned eCount);
 
-        void
-        serialize(CheckpointOut &cp) const override
-        {
-            DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
-            SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
-        }
-
-        void
-        unserialize(CheckpointIn &cp) override
-        {
-            DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
-            UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
-            CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
-            updateRegMap(tmp_cpsr);
-        }
+        void serialize(CheckpointOut &cp) const override;
+        void unserialize(CheckpointIn &cp) override;
 
         void startup() override;