dev,stats: Update stats style for CopyEngine and IdeDisk
Change-Id: Ib757b00864bc144b20adef974e3443ddba2945f0 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36436 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
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@@ -58,7 +58,8 @@
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using namespace CopyEngineReg;
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CopyEngine::CopyEngine(const Params &p)
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: PciDevice(p)
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: PciDevice(p),
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copyEngineStats(this, p.ChanCnt)
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{
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// All Reg regs are initialized to 0 by default
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regs.chanCount = p.ChanCnt;
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@@ -425,23 +426,20 @@ CopyEngine::CopyEngineChannel::channelWrite(Packet *pkt, Addr daddr, int size)
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}
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}
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void
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CopyEngine::regStats()
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CopyEngine::
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CopyEngineStats::CopyEngineStats(Stats::Group *parent,
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const uint8_t &channel_count)
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: Stats::Group(parent, "CopyEngine"),
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ADD_STAT(bytesCopied, "Number of bytes copied by each engine"),
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ADD_STAT(copiesProcessed, "Number of copies processed by each engine")
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{
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PciDevice::regStats();
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using namespace Stats;
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bytesCopied
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.init(regs.chanCount)
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.name(name() + ".bytes_copied")
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.desc("Number of bytes copied by each engine")
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.flags(total)
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.init(channel_count)
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.flags(Stats::total)
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;
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copiesProcessed
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.init(regs.chanCount)
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.name(name() + ".copies_processed")
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.desc("Number of copies processed by each engine")
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.flags(total)
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.init(channel_count)
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.flags(Stats::total)
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;
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}
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@@ -521,8 +519,8 @@ CopyEngine::CopyEngineChannel::writeCopyBytes()
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cePort.dmaAction(MemCmd::WriteReq, ce->pciToDma(curDmaDesc->dest),
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curDmaDesc->len, &writeCompleteEvent, copyBuffer, 0);
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ce->bytesCopied[channelId] += curDmaDesc->len;
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ce->copiesProcessed[channelId]++;
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ce->copyEngineStats.bytesCopied[channelId] += curDmaDesc->len;
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ce->copyEngineStats.copiesProcessed[channelId]++;
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}
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void
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@@ -139,8 +139,13 @@ class CopyEngine : public PciDevice
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private:
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Stats::Vector bytesCopied;
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Stats::Vector copiesProcessed;
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struct CopyEngineStats : public Stats::Group
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{
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CopyEngineStats(Stats::Group *parent, const uint8_t& channel_count);
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Stats::Vector bytesCopied;
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Stats::Vector copiesProcessed;
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} copyEngineStats;
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// device registers
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CopyEngineReg::Regs regs;
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@@ -158,8 +163,6 @@ class CopyEngine : public PciDevice
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CopyEngine(const Params ¶ms);
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~CopyEngine();
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void regStats() override;
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Port &getPort(const std::string &if_name,
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PortID idx = InvalidPortID) override;
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@@ -60,6 +60,7 @@
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IdeDisk::IdeDisk(const Params &p)
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: SimObject(p), ctrl(NULL), image(p.image), diskDelay(p.delay),
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ideDiskStats(this),
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dmaTransferEvent([this]{ doDmaTransfer(); }, name()),
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dmaReadCG(NULL),
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dmaReadWaitEvent([this]{ doDmaRead(); }, name()),
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@@ -386,37 +387,18 @@ IdeDisk::doDmaDataRead()
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schedule(dmaReadWaitEvent, curTick() + totalDiskDelay);
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}
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void
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IdeDisk::regStats()
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IdeDisk::
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IdeDiskStats::IdeDiskStats(Stats::Group *parent)
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: Stats::Group(parent, "IdeDisk"),
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ADD_STAT(dmaReadFullPages,
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"Number of full page size DMA reads (not PRD)."),
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ADD_STAT(dmaReadBytes,
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"Number of bytes transfered via DMA reads (not PRD)."),
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ADD_STAT(dmaReadTxs, "Number of DMA read transactions (not PRD)."),
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ADD_STAT(dmaWriteFullPages, "Number of full page size DMA writes."),
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ADD_STAT(dmaWriteBytes, "Number of bytes transfered via DMA writes."),
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ADD_STAT(dmaWriteTxs, "Number of DMA write transactions.")
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{
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SimObject::regStats();
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using namespace Stats;
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dmaReadFullPages
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.name(name() + ".dma_read_full_pages")
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.desc("Number of full page size DMA reads (not PRD).")
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;
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dmaReadBytes
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.name(name() + ".dma_read_bytes")
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.desc("Number of bytes transfered via DMA reads (not PRD).")
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;
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dmaReadTxs
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.name(name() + ".dma_read_txs")
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.desc("Number of DMA read transactions (not PRD).")
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;
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dmaWriteFullPages
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.name(name() + ".dma_write_full_pages")
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.desc("Number of full page size DMA writes.")
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;
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dmaWriteBytes
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.name(name() + ".dma_write_bytes")
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.desc("Number of bytes transfered via DMA writes.")
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;
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dmaWriteTxs
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.name(name() + ".dma_write_txs")
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.desc("Number of DMA write transactions.")
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;
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}
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void
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@@ -445,10 +427,10 @@ IdeDisk::doDmaRead()
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assert(dmaReadCG->complete() < MAX_DMA_SIZE);
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ctrl->dmaRead(pciToDma(dmaReadCG->addr()), dmaReadCG->size(),
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&dmaReadWaitEvent, dataBuffer + dmaReadCG->complete());
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dmaReadBytes += dmaReadCG->size();
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dmaReadTxs++;
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ideDiskStats.dmaReadBytes += dmaReadCG->size();
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ideDiskStats.dmaReadTxs++;
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if (dmaReadCG->size() == chunkBytes)
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dmaReadFullPages++;
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ideDiskStats.dmaReadFullPages++;
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dmaReadCG->next();
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} else {
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assert(dmaReadCG->done());
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@@ -530,10 +512,10 @@ IdeDisk::doDmaWrite()
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&dmaWriteWaitEvent, dataBuffer + dmaWriteCG->complete());
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DPRINTF(IdeDisk, "doDmaWrite: not done curPrd byte count %d, eot %#x\n",
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curPrd.getByteCount(), curPrd.getEOT());
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dmaWriteBytes += dmaWriteCG->size();
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dmaWriteTxs++;
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ideDiskStats.dmaWriteBytes += dmaWriteCG->size();
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ideDiskStats.dmaWriteTxs++;
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if (dmaWriteCG->size() == chunkBytes)
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dmaWriteFullPages++;
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ideDiskStats.dmaWriteFullPages++;
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dmaWriteCG->next();
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} else {
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DPRINTF(IdeDisk, "doDmaWrite: done curPrd byte count %d, eot %#x\n",
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@@ -252,12 +252,17 @@ class IdeDisk : public SimObject
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/** DMA Aborted */
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bool dmaAborted;
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Stats::Scalar dmaReadFullPages;
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Stats::Scalar dmaReadBytes;
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Stats::Scalar dmaReadTxs;
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Stats::Scalar dmaWriteFullPages;
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Stats::Scalar dmaWriteBytes;
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Stats::Scalar dmaWriteTxs;
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struct IdeDiskStats : public Stats::Group
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{
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IdeDiskStats(Stats::Group *parent);
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Stats::Scalar dmaReadFullPages;
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Stats::Scalar dmaReadBytes;
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Stats::Scalar dmaReadTxs;
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Stats::Scalar dmaWriteFullPages;
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Stats::Scalar dmaWriteBytes;
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Stats::Scalar dmaWriteTxs;
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} ideDiskStats;
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public:
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typedef IdeDiskParams Params;
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@@ -273,11 +278,6 @@ class IdeDisk : public SimObject
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*/
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void reset(int id);
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/**
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* Register Statistics
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*/
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void regStats() override;
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/**
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* Set the controller for this device
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* @param c The IDE controller
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