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arch-gcn3: Implement s_setreg_imm32_b32 instruction

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Change-Id: I5383243403156dc17d4997106085a62fb0483fec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37475
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Kyle Roarty
2020-11-10 00:08:18 -06:00
parent b0dbc09b3f
commit c1ddd01b66
1 changed files with 23 additions and 0 deletions
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23
src/arch/gcn3/insts/instructions.cc
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@@ -1847,6 +1847,7 @@ namespace Gcn3ISA
InFmt_SOPK *iFmt)
: Inst_SOPK(iFmt, "s_setreg_imm32_b32")
{
setFlag(ALU);
} // Inst_SOPK__S_SETREG_IMM32_B32
Inst_SOPK__S_SETREG_IMM32_B32::~Inst_SOPK__S_SETREG_IMM32_B32()
@@ -1860,6 +1861,28 @@ namespace Gcn3ISA
void
Inst_SOPK__S_SETREG_IMM32_B32::execute(GPUDynInstPtr gpuDynInst)
{
ScalarRegI16 simm16 = instData.SIMM16;
ScalarRegU32 hwregId = simm16 & 0x3f;
ScalarRegU32 offset = (simm16 >> 6) & 31;
ScalarRegU32 size = ((simm16 >> 11) & 31) + 1;
ScalarOperandU32 hwreg(gpuDynInst, hwregId);
ScalarRegU32 simm32 = extData.imm_u32;
hwreg.read();
ScalarRegU32 mask = (((1U << size) - 1U) << offset);
hwreg = ((hwreg.rawData() & ~mask)
| ((simm32 << offset) & mask));
hwreg.write();
if (hwregId==1 && size==2
&& (offset==4 || offset==0)) {
warn_once("Be cautious that s_setreg_imm32_b32 has no real effect "
"on FP modes: %s\n", gpuDynInst->disassemble());
return;
}
// panic if not changing MODE of floating-point numbers
panicUnimplemented();
}