Commit Graph

976 Commits

Author SHA1 Message Date
huangjs
ea6b0a03d3 mem: Setup stats for Cache hitLatency
Change-Id: I18de75d3b6c4ce1784b90653e2d132ffecf1b1af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53103
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-11-30 02:59:05 +00:00
huangjs
cdbeb07ffd mem: Targets per MSHR allocated should be always <= tgts_per_mshr
This modification indicates when tgts_per_mshr = 0 for particular level of Cache

Change-Id: Icc1ecffcd598a473bd26bc5115a5e0a7998fb527
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52783
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-22 01:31:02 +00:00
Gabe Black
ba5f68db3d misc: Use python 3's argumentless super().
When calling a method in a superclass, you can/should use the super()
method to get a reference to that class. The python 2 version of that
method takes two parameters, the current class name, and the "self"
instance. The python 3 version takes no arguments. This is better for a
at least three reasons.

First, this version is less verbose because you don't have to specify
any arguments.

Second, you don't have to remember which argument goes where (I always
have to look it up), and you can't accidentally use the wrong class
name, or forget to update it if you copy code from a different class.

Third, this version will work correctly if you use a class decorator.
I don't know exactly how the mechanics of this work, but it is referred
to in a comment on this stackoverflow question:

https://stackoverflow.com/questions/681953/how-to-decorate-a-class

Change-Id: I427737c8f767e80da86cd245642e3b057121bc3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52224
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-09 13:04:44 +00:00
Gabe Black
e34fa5d86a mem-cache: Ensure all fields of the CacheBlk class are initialized.
The constructor only initialized two fields, data and _tickInserted. The
print() method at least accesses the coherence status bits, which
valgrind determined were being accessed without being initialized.

This change adds a default initializer to all fields to prevent any
value from flapping around uninitialized.

Change-Id: Ie4c839504d49f9a131d8e3c3e8be02ff22f453a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52404
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-04 22:53:51 +00:00
Gabe Black
6d60e76a60 mem-cache: Don't generate debug output unless you're going to use it.
The BaseCache::handleFill function would generate an "old_state" string
unconditionally, just in case it would need to print it out later on in
the function if the Cache debug variable was set. This is very wasteful.
We should only generate that string if we are actually going to use it
later on.

Change-Id: I4a570d1cd2814e5a089eac1233dedd1801d68975
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52405
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-04 19:48:08 +00:00
Gabe Black
7290bf52f3 mem: Replace SatCounter with SatCounter8 in the SHiP replacement policy.
Change-Id: Ibbc8e78df7119cdff62ad08b5c68f4237ca25cfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51530
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 23:13:57 +00:00
Gabe Black
d6974ef636 mem: Add a page_bytes parameter to the classic prefetcher.
This parameter is used to figure out if two addresses are on the same or
different pages, and could be used to find what page they were on and
the page offset, although it doesn't look like the later two are
actually used.

This value could possibly come from the TLB parameter attached to the
prefetcher, but making it explicit makes these more symmetric with the
Ruby prefetcher, and reduces the complexity of the TLB implementation.

Change-Id: I6921943c49af19971b84225ecfd1127304363426
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50352
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-09-30 00:31:29 +00:00
Gabe Black
e90cb8ab75 mem,sim: Replace the deprecated chatty_assert with gem5_assert.
The new gem5_assert macro now does the job of both regular asserts, and
chatty_assert, except that its condition must always be valid code. It
is still not evaluated if NDEBUG is set, though.

Change-Id: I7c9435311746b2e02fe7335bce6ba618bf9fd4eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48607
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-08-21 00:54:54 +00:00
Nathanael Premillieu
2462e650ba mem-cache: reuse local variable in QueuedPrefetcher
Reuse local variable for PA in Queued::translationComplete.

Change-Id: Id3c0333ac1bf019ac21162aedf69f6019c818e30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48684
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2021-07-30 13:13:37 +00:00
Nathanael Premillieu
393a964266 mem-cache: print VA and PA in the prefetch queues
As prefetcher can use VA and need translation, it is
interesting to see both VA and PA when printing the queues.
PA is printed as 0 if translation has not happened yet.
Also fix a bug when the pkt is not yet created.

Change-Id: I7cd225379c2930a8d6a7882efdb3dc7bc49fb8a3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48683
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2021-07-30 07:35:48 +00:00
Gabe Black
00876fff20 misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
The [[maybe_unused]] attribute is now standard, so we can use that
directly without hiding it behind a macro.

Change-Id: If24ffd7e50bdb503cb3e6ea61f226ea794e84b8f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48511
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-29 10:17:51 +00:00
Gabe Black
b3b81196aa misc: Replace type_traits.hh XX::value with XX_v.
Now that we're using c++17, the type_traits with a ::value member have
a _v alias which reduces verbosity. Or on other words

std::is_integral<T>::value

can be replaced with

std::is_integral_v<T>

Make this substitution throughout the code base. In places where gem5
introduced it's own similar templates, add a V alias, spelled
differently to match gem5's internal style.

gem5: :IsVarArgs<T>::value => gem5::IsVarArgsV<T>
Change-Id: I1d84ffc4a236ad699471569e7916ec17fe5f109a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48604
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-28 01:48:03 +00:00
Gabe Black
2f42e79956 mem: Use the new "debug" namespace, and not "Debug".
The "Debug" namespace is deprecated and has been replaced by "debug".

Change-Id: Ic8e9082361a6717f3b07990dbaa1a66b0926f000
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48647
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-27 21:32:21 +00:00
Gabe Black
59496b6136 mem,gpu-compute: Stop using the GEM5_NO_DISCARD macro.
The [[nodiscard]] attribute is now standard, so we can use that
directly.

Change-Id: I57f59935858facb2a15bf4712be4bfd584bf0c7e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48509
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-24 21:57:04 +00:00
Nathanael Premillieu
5c7e1bd917 mem-cache: adding late prefetch stats
Adding a late prefetch stat plus stats for each reason a prefetch can be
detected as late

Change-Id: Ia6d5294e8ce58b2b0aae2be98fd0cee83be73b8d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47204
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-09 22:30:45 +00:00
Nathanael Premillieu
0339f34b87 mem-cache: count pf filtered by demand to the same cache line
Add a stat to count how many prefetch request are filtered in the
prefetch queue becasue a demand is going to the same cache line
Also adding a corresponding debug statement for when it happens

Change-Id: I52475f19bd109c135b7259d08d5f5c0b5fd90ee5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47203
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-07-09 22:30:45 +00:00
Nathanael Premillieu
de80da9204 mem-cache: show in DPPRINTF if block is prefetched
Add the prefetch status in the DPRINTF showing the
state of a cache block.

Change-Id: Ib8edf882dc17414f751cc8773d9035ee2887e971
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47202
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-07-09 22:30:45 +00:00
Nathanael Premillieu
b193c0adfd mem-cache: add option to send pf on hit on pf
From the point of view of the prefetchers, a hit on a prefetched block
should be considered the same as a miss: a new prefetch should be
generated.

Change-Id: If865324502b81cfd3ae8c009666d3f498092b90f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47201
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2021-07-09 22:30:45 +00:00
Nathanael Premillieu
352ae672e2 mem-cache: accuracy and coverage stat for prefetchers
Add an accuracy and coverage stat for the prefetchers.
Accuracy is defined as the ratio of the number of prefetch
request that have been counted as useful over the number
of prefetch request issued.
Accuracy tells whether the prefetcher is producing useful
requests or not.
Coverage is defined as the ratio of of the number of prefetch
request that have been counted as useful over the number of
demand misses if there was no prefetch, which is counted as
the number of useful prefetch request plus the remaining
demand misses. Due to the way stats are defined in the cache,
I have to add a stat to count the number of remaining demand
misses directly in the prefetcher stat. Demand is defined
as being one of this request type: ReadReq, WriteReq,
WriteLineReq, ReadExReq, ReadCleanReq, ReadSharedReq.
Coverage tells what part of misses are covered by the prefetcher.

Change-Id: I3bb8838f87b42665fdd782889f6ba56ca2a802fc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47603
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-09 22:30:45 +00:00
Nathanael Premillieu
c66f32f24e mem-cache: add a prefetch useful stat
Count how many time a prefetch is useful, meaning
a hit has happened on a prefetched cache block.
Another stat (pfUsefulButMiss) has been added to count
the special case where there is a hit on prefetched block
but it is counted as a miss because the block is not in
the requested coherency state.

Change-Id: I253216b9ac96d5f21139b710c489d6eb3fce7136
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47602
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-09 22:30:45 +00:00
Nathanael Premillieu
f691613876 mem-cache: print when hitting on a prefetched line
Only print it on the first it on a prefetched line
(as the prefetched flag is removed after the first hit)
This is useful when debugging prefetchers.

Change-Id: Id67cc957c7366a244bedad93824a3c4fdf2055b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47601
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2021-07-09 22:30:45 +00:00
Nathanael Premillieu
cf0881433b mem-cache: add pfIssued stat in MultiPrefetcher
Count issued prefetches for each prefetchter in a MultiPrefetcher

Change-Id: If03fb0669af9bb92ce9cf210b6201a9719a7c771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47600
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2021-07-09 22:30:45 +00:00
Nathanael Premillieu
85a8dbf761 mem-cache: move unusedPrefetches stat to prefetcher
This stat belongs to prefetchers.
It has been renamed to pfUnused to match the naming of
exisiting prefetcher stats.

Change-Id: Iec350a62da544535dfc0c2527fcdf73217ae4db7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47599
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-09 22:30:45 +00:00
Nathanael Premillieu
f3e7d02150 mem-cache: print prefetch queues in Queued prefetcher
Added to track the content of the prefetch queues in the debug output

Change-Id: I49d0f4f643ec0dbd7af3087b6267d454cfccddba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47199
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-09 22:30:45 +00:00
Giacomo Travaglini
d1cdcb311b misc: Move Mode and Translation from BaseTLB to BaseMMU
This is a step towards moving most of the TLB logic to the
MMU class.

Change-Id: Id6b1fb30aa89960705f165f9738f5b50aa1e6bdb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46779
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-07 08:44:13 +00:00
Gabe Black
d58b4f004e misc: Remove typedef (struct|enum) Foo in cpp files.
In C, to refer to a type without a struct or enum tag on the type, you
need to typedef it like this:

typedef struct
{
} Foo;

Foo foo;

In C++, this is unnecessary:

struct Foo
{
};

Foo foo;

Remove all of the first form in C++ files and replace them with the
second form.

Change-Id: I37cc0d63b2777466dc6cc51eb5a3201de2e2cf43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46199
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-07 08:35:12 +00:00
Daniel R. Carvalho
4b2118ed4b misc: Remove sim/cur_tick dependency from sim/core.hh
Remove this unnecessary dependency. Fixed all incorrect
includes of sim/core.hh.

Change-Id: I3ae282dbaeb45fbf4630237a3ab9b1a593ffbe0c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43592
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-06 09:59:11 +00:00
Daniel R. Carvalho
974a47dfb9 misc: Adopt the gem5 namespace
Apply the gem5 namespace to the codebase.

Some anonymous namespaces could theoretically be removed,
but since this change's main goal was to keep conflicts
at a minimum, it was decided not to modify much the
general shape of the files.

A few missing comments of the form "// namespace X" that
occurred before the newly added "} // namespace gem5"
have been added for consistency.

std out should not be included in the gem5 namespace, so
they weren't.

ProtoMessage has not been included in the gem5 namespace,
since I'm not familiar with how proto works.

Regarding the SystemC files, although they belong to gem5,
they actually perform integration between gem5 and SystemC;
therefore, it deserved its own separate namespace.

Files that are automatically generated have been included
in the gem5 namespace.

The .isa files currently are limited to a single namespace.
This limitation should be later removed to make it easier
to accomodate a better API.

Regarding the files in util, gem5:: was prepended where
suitable. Notice that this patch was tested as much as
possible given that most of these were already not
previously compiling.

Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46323
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-01 19:08:24 +00:00
Daniel R. Carvalho
24041d6b77 mem-cache: Add Signature-Based Hit Predictor replacement policy
Add the SHiP Replacement Policy, as described in "SHiP: Signature-
based Hit Predictor for High Performance Caching", by Wu et al.

Instruction Sequence signatures have not been implemented.

Change-Id: I44f00d26eab4c96c9c5bc29740862a87356d30d1
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38118
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-07-01 11:21:30 +00:00
Daniel R. Carvalho
4a3e99fbcb mem-cache: Allow sending packet information to replacement policy
Some replacement policies can use information such as address or
PC to improve their re-reference prediction.

Change-Id: I412eee09efa2f3511ca1ece76fc2732509df4745
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38117
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2021-07-01 11:21:30 +00:00
Daniel R. Carvalho
ef99dc8310 mem-cache: Use PacketPtr in tags's accessBlock
Pass the packet to the tags, so that the replacement policies
more execution information.

Change-Id: I201884a6d60e3299fc3c9befebbb2e8b64a007f0
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38116
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2021-07-01 11:21:30 +00:00
Daniel R. Carvalho
2911839c22 mem-cache: Make WeightedLRU inherit from LRU
WeightedLRU adds occupancy information to LRU, so remove the
duplicated code.

Change-Id: Ifec19ea59fb411a5ed7a891e8957b1ab93cdbf05
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47399
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2021-07-01 11:21:30 +00:00
Daniel R. Carvalho
041134e8d9 mem-cache: Change invalidate signature to not const
Allow the replacement policy to be modified when an entry is
invalidated.

Change-Id: I7f5086795dbb93a6fab2b4994c757d509d782d79
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38115
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2021-06-30 02:11:56 +00:00
Daniel R. Carvalho
3f040bab87 mem-cache: Add the DRRIP replacement policy
Instantiate the Dynamic Re-Reference Interval Prediction, as defined
in "High Performance Cache Replacement Using Re-Reference Interval
Prediction (RRIP)", by Jaleel et al.

Change-Id: Id1d354c01e63ae49739263647ff25e5665f60d8c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37898
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-06-30 02:11:56 +00:00
Daniel R. Carvalho
fd79a761ad mem-cache: Implement a dueling Replacement Policy
Implement a template dueling replacement policy which monitors
two replacement policies to decide and select the one that
provides the least amount of misses.

Change-Id: I6a6e96a9388cce8f8c8cd7b9c1dbe9f0554ccc64
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37897
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-30 02:11:56 +00:00
Daniel R. Carvalho
df5b191609 mem-cache: Creation of dueling classes
Table policies (i.e., replacement, compression, etc) behave
differently depending on the workload, and it is often desired
to be able to selectively switch between them. In this case
the relevant metadata for all the policies must be added to
all of the entries being analyzed.

In order to avoid having to monitor all table entries, a few
of these entries are selected to be sampled and estimate
overall behavior. These sampled entries belong each to a
single policy. Then, based on the predominance of these
samples, the winning policy is applied to the other sets
(followers).

As of now, in order to avoid having to iterate over a vector,
there is a limited number of dueling instances, but it may be
easily extended, if needed.

Based on Set Dueling, proposed in "Adaptive Insertion Policies
for High Performance Caching".

Change-Id: I692a3e5e0ad98581d68167ad7e6b45ab2f4c7b10
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37895
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-06-30 02:11:56 +00:00
Tom Rollet
3beeea0f40 mem-cache: Add MSHR debuging information
Add debug statment in MSHR and MSHRQueue class to track the
number of free MSHR each time a new one is allocated/deallocated.

Also track the allocation/deallocation of each MSHR target.

Change-Id: I2533e7660da1cde3052425f8db8852e59d463b42
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47041
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-29 07:06:30 +00:00
Tom Rollet
15cba2ad1c mem-cache: Queue,QueueEntry, NSHR::TargetList inherit from Named
With this change, when using a DPRINTF statment on a class inheriting
from the Queue or QueueEntry class, the name at the start of the log
line will be meaningful.

Currently affected classes:
    MSHRqueue
    MSHR
    MSHR::TargetList
    WriteQueue
    WriteQueueEntry

Change-Id: I4e5ac080fec572961f9f1d9f88429ed6e72d8994
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-29 07:06:18 +00:00
Tom Rollet
37635f290d mem-cache: change Cache debug flag to MSHR in MSHR code
Change-Id: I97ba0d5426d51d913649dcabb6d1ca862e4d137a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47039
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-29 07:06:18 +00:00
sacak32
b0f534346a mem-cache: queued prefetcher bug fix
In queued prefetcher, addToQueue function doesn't behave
correctly where the element must be added to the end of queue.
I fixed this bug.

Change-Id: I1eec129f827b6465e7cef874c551d96acbf18d5b
Signed-off-by: Burak Öçalan <byrakocalan99@gmail.com>
Reported-by: Burak Öçalan <byrakocalan99@gmail.com>
Tested-by: Burak Öçalan <byrakocalan99@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46759
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-12 08:21:04 +00:00
Arthur Perais
c01b9cd62b mem: Fix bandwidth-delay calculation in AMPM prefetcher
The AMPM paper (https://www.jilp.org/vol13/v13paper3.pdf) defines
the bandwidth-delay calculation as :

  Mbandwidth= (Nrequests/Tepoch)×Tlatency

In the code, Tepoch and Tlatency are in ticks (which is okay),
but Tepoch is converted from Cycles (256K) to Ticks using the
clockEdge(Cycle c) function, which is incorrect as it yields currentTick
+ c * clockPeriod() instead of just c * clockPeriod().
In other words, the divider keeps increasing as time advances.

This patch substitutes clockEdge() with cyclesToTicks() to keep
the epoch length (Tepoch) constant throughout simulation.

Change-Id: I69dee29892fa4b9eb8de8715fd72a535e122687f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46479
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-05 16:24:41 +00:00
Arthur Perais
efc9a68620 mem: Fix Best Offset Prefetcher (BOP) learning phase code.
According to the DPC paper : "If the best score is less
than or equal to a fixed value BADSCORE, we turn prefetchoff
during the next phase"

However, the current code will turn prefetch off if the best
*offset* of the learning phase is less than BADSCORE, which
is incorrect.

Change-Id: Ib5790fe1341f2dd6328ec3b018bc52012e376723
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46259
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-06-01 19:36:20 +00:00
Daniel R. Carvalho
98ac080ec4 base-stats,misc: Rename Stats namespace as statistics
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Stats became ::statistics.

"statistics" was chosen over "stats" to avoid generating
conflicts with the already existing variables (there are
way too many "stats" in the codebase), which would make
this patch even more disturbing for the users.

Change-Id: If877b12d7dac356f86e3b3d941bf7558a4fd8719
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45421
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
4dd099ba3d misc: Rename Enums namespace as enums
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Enums became ::enums.

Change-Id: I39b5fb48817ad16abbac92f6254284b37fc90c40
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45420
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
e291376f07 cpu,mem: Rename ContextSwitchTaskId namespace
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::ContextSwitchTaskId becomes ::context_switch_task_id.

Change-Id: If3884a5da7afe6144954d556b3b54f659bb7afb5
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45411
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
df72e9d548 mem-cache: Rename Prefetcher namespace as prefetch
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Prefetcher became ::prefetcher.

"prefetch" was chosen over "prefetcher" to avoid generating
conflicts with the already existing variables. "prefetcher"
is a name that is expected to be more common in user's code
than "prefetch".

Change-Id: I8f07217f278a0229e05545b7847f2620ed208c66
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45410
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-29 11:13:49 +00:00
Daniel R. Carvalho
2a0e4ae3ea mem-cache: Rename Encoder namespace as encoder
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

compression::Encoder became compression::encoder.

Change-Id: I3ff2693fbbfc366952cf0f03414a00debae27635
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45408
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-28 23:01:26 +00:00
Daniel R. Carvalho
c84888b67a mem-cache: Rename encoder variables as indexEncoder
Pave the way for an encoder namespace.

Change-Id: I5b55ac18a2973e25e53b097cd407861f5f60d646
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45407
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-28 23:01:26 +00:00
Daniel R. Carvalho
495f0cb63d mem-cache: Rename Compressor namespace as compression
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Compressor became ::compression.

"compression" was chosen over "compressor" to avoid
generating conflicts with the already existing variables,
as well as because the namespace contains more than solely
compressors (e.g., encoders).

Change-Id: I7054845984784b0dffcc4fb90d66c5096a64194d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45406
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-28 23:01:26 +00:00
Daniel R. Carvalho
17897bb3f6 mem: Rename ReplacementPolicy namespace as replacement_policy
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::ReplacementPolicy became ::replacement_policy.

Change-Id: Id46cd9d89e9424fd3c5484e2f9c69ef2b73f135b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45405
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-05-27 08:32:55 +00:00