The system calls had four parameters. One of the parameters
is ThreadContext and another is Process. The ThreadContext
holds the value of the current process so the Process parameter
is redundant since the system call functions already have
indirect access.
With the old API, it is possible to call into the functions with
the wrong supplied Process which could end up being a confusing
error.
This patch removes the redundancy by forcing access through the
ThreadContext field within each system call.
Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
ARMv8.2 16-bit versions have not yet been implemented, but a placeholders
were created for them.
Refactor the nearby decoding tree to closely match the ARM spec A32 decode
table.
That piece of the tree can also be called from thumb which decodes it in
the same way, although the thumb decode table has a different terminology
The old code didn't match neither A32 or T32 terminologies, so it is
better to at least match one of them to help verify correctness.
Change-Id: Iabbbca2932557cf6c98ce36690c385c3ddf39ed8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18690
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
c_j(al) has a special format, called CJ.
The jump offset format is instbits[12:2] --> offset[11|4|9:8|10|6|7|3:1|5]
Currently in decoder.isa, c_j format is JOp, the imm and branchTarget are incorrect
In the execute section (decoder.isa:228), the imm fields is ignored and the offset is calculated correctlly.
As a result, we get decoder flush for each c_j instance
I've added CJOp format in compressed.isa, and use it in execute section.
In addition, c_j is mappped to jal zero, cj_imm, and actually is neither indirect control nor a function call
I fixed the flags accordently.
I'll fix all IsRet, IsCall and IsIndirectControl flags for rest of (c_)jal(r) in my next commit.
I ran coremark -O0 before my fix and I got 37.7% branch miss-rate, after the fix the branch miss-rate is <13%
Change-Id: I608d5894a78a1ebefe36f21e21aaea68b42bccfc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17808
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
This doesn't need to be plumbed through generic interfaces. If the
function/instruction got more complex in the future (unlikely since
Alpha doesn't really see development these days), it could be moved to
a helper function defined within Alpha files.
Change-Id: Ib746fad7bb13c5cc9c6ee555c3a46ce686771c12
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18433
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Then cast to the ISA specific type when necessary. This removes
(mostly) an ISA specific aspect to some of the interfaces. The ISA
specific version of the kernel stats still needs to be constructed and
stored in a few places which means that kernel_stats.hh still needs to
be a switching arch header, for instance.
In the future, I'd like to make the kernel its own object like the
Process objects in SE mode, and then it would be able to instantiate
and maintain its own stats.
Change-Id: I8309d49019124f6bea1482aaea5b5b34e8c97433
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18429
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
These accessors can be implemented as helper functions within MIPS
without having to plumb them through a bunch of common interfaces.
There are a few problems with the way they were implemented which are
carried forward to this new implementation as well. That includes
hiding the register accesses from the ISA parser and therefore the
CPU's dependency tracking, potentially panicing or accessing a non
existent thread based on a possible set of input values, and modifying
register values even if an instruction is being executed speculatively.
Fixing these problems would be fairly involved and require changing how
dependencies are tracked in all the CPUs so that they can act across
threads, and also how registers are handled in the ISA description
itself.
The original implementation just punted on making this work in CPUs
other than the minor CPU (and potentially one or more CPU models that
were not and/or are not in the code base). Where as that implementation
might have paniced if these methods were called, this will attempt to
work, but may have incorrect behavior based on the limitations
described above. I'd consider this an acceptable tradeoff, at least for
the time being.
Change-Id: I94adceafb9812a8641c76ea3518c3285c31baf51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18435
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
When dumping the opcode that caused an Undefined Instruction, we just
want to dump the real instruction encoding, and not the extended version
with metabits (like thumb, bigThumb etc). This was not appening when
panicking in SE mode.
The patch is also replacing custom masking in the Unknown(64) disassembler
in favour of ArmStaticInstruction::encoding() helper.
Change-Id: I9eb6fd145d02b4b07bb51f0bd89ca014d6d5a6de
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18395
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
The AuxVector type has a bunch of accessors which just give access to
the underlying variables through references. We might as well just make
those members accessible directly.
Also, the AuxVector doesn't need to handle endianness flips itself. We
can tell the byteswap mechanism how to flip an AuxVector, and let it
handle that for us.
This gets rid of the entire .cc file which was complicated by trying
to both hide the ISA specific endianness translations, and instantiate
templated functions in a .cc.
Change-Id: I433cd61e73e0b067b6d628fba31be4a4ec1c4cf0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18373
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
These selected their behavior based on ifdefs and had to be disabled
when on the NULL ISA. The versions which take an explicit endianness
have been renamed to just read/write instead of readGtoH and writeHtoG
since the direction of the translation is obvious from context.
Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18372
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.
Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
This changeset enables clone to work with X86KvmCPU model, which
will allow running multi-threaded applications at near hardware
speeds. Even though the application is multi-threaded, the KvmCPU
model uses one event queue, therefore, only one hardware thread
will be used, through KVM, to simulate multiple application threads.
Change-Id: I2b2a7b1edb1c56eeb9c4fa0553cd236029cd53f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18268
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
