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arch: Stop using TheISA within the ISAs.

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We know for sure what the ISA is, so there's no need for the
indirection.

Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18488
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2019-04-29 17:12:08 -07:00
parent ecd6be3d11
commit 12eab3e7a6
20 changed files with 58 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/alpha/utility.cc
View File

@@ -100,7 +100,7 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest)
void
skipFunction(ThreadContext *tc)
{
TheISA::PCState newPC = tc->pcState();
PCState newPC = tc->pcState();
newPC.set(tc->readIntReg(ReturnAddressReg));
tc->pcState(newPC);
}

2
src/arch/arm/isa/insts/fp64.isa
View File

@@ -45,7 +45,7 @@ let {{
exec_output = ""
zeroSveVecRegUpperPartCode = '''
TheISA::ISA::zeroSveVecRegUpperPart(%s,
ArmISA::ISA::zeroSveVecRegUpperPart(%s,
ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
'''

6
src/arch/arm/isa/insts/ldr64.isa
View File

@@ -185,7 +185,7 @@ let {{
accCode = 'uint64_t temp M5_VAR_USED = Mem%s;'
elif self.flavor == "fp":
accEpilogCode = '''
TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
ArmStaticInst::getCurSveVecLen<uint64_t>(
xc->tcBase()));
'''
@@ -239,10 +239,10 @@ let {{
# Code that actually handles the access
if self.flavor == "fp":
accEpilogCode = '''
TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
ArmStaticInst::getCurSveVecLen<uint64_t>(
xc->tcBase()));
TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2,
ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2,
ArmStaticInst::getCurSveVecLen<uint64_t>(
xc->tcBase()));
'''

2
src/arch/arm/isa/insts/neon64_mem.isa
View File

@@ -45,7 +45,7 @@ let {{
exec_output = ''
zeroSveVecRegUpperPartCode = '''
TheISA::ISA::zeroSveVecRegUpperPart(%s,
ArmISA::ISA::zeroSveVecRegUpperPart(%s,
ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
'''

48
src/arch/arm/isa/insts/sve.isa
View File

@@ -1555,7 +1555,7 @@ let {{
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
TheISA::VecRegContainer tmpVecC;
ArmISA::VecRegContainer tmpVecC;
auto auxOp1 = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
auxOp1[i] = AA64FpOp1_x[i];
@@ -1616,7 +1616,7 @@ let {{
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
TheISA::VecRegContainer tmpVecC;
ArmISA::VecRegContainer tmpVecC;
auto tmpVec = tmpVecC.as<Element>();
int ePow2Count = 1;
while (ePow2Count < eCount) {
@@ -1761,7 +1761,7 @@ let {{
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
TheISA::VecRegContainer tmpVecC;
ArmISA::VecRegContainer tmpVecC;
auto auxOp2 = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; i++) {
auxOp2[i] = AA64FpOp2_ud[i];
@@ -1917,7 +1917,7 @@ let {{
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
TheISA::VecPredRegContainer tmpPredC;
ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; i++) {
auxGpOp[i] = GpOp_x[i];
@@ -1981,7 +1981,7 @@ let {{
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
TheISA::VecPredRegContainer tmpPredC;
ArmISA::VecPredRegContainer tmpPredC;
auto tmpPred = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i)
tmpPred[i] = GpOp_x[i];
@@ -2140,7 +2140,7 @@ let {{
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
TheISA::VecPredRegContainer tmpPredC;
ArmISA::VecPredRegContainer tmpPredC;
auto tmpPred = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i)
tmpPred[i] = GpOp_x[i];
@@ -2185,7 +2185,7 @@ let {{
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
TheISA::VecPredRegContainer tmpPredC;
ArmISA::VecPredRegContainer tmpPredC;
auto tmpPred = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i)
tmpPred[i] = GpOp_x[i];
@@ -2268,7 +2268,7 @@ let {{
unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
xc->tcBase());
bool dobreak = false;
TheISA::VecPredRegContainer tmpPredC;
ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<uint8_t>();
for (unsigned i = 0; i < eCount; ++i) {
auxGpOp[i] = GpOp_ub[i];
@@ -2320,7 +2320,7 @@ let {{
unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
xc->tcBase());
bool last = POp1_ub.lastActive(GpOp_ub, eCount);
TheISA::VecPredRegContainer tmpPredC;
ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<uint8_t>();
for (unsigned i = 0; i < eCount; ++i) {
auxGpOp[i] = GpOp_ub[i];
@@ -2458,7 +2458,7 @@ let {{
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
TheISA::VecPredRegContainer tmpPredC;
ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
auxGpOp[i] = GpOp_x[i];
@@ -2500,7 +2500,7 @@ let {{
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
TheISA::VecPredRegContainer tmpPredC;
ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i)
auxGpOp[i] = GpOp_x[i];
@@ -2568,14 +2568,14 @@ let {{
if unpackHalf == Unpack.Low:
if regType == SrcRegType.Predicate:
code += '''
TheISA::VecPredRegContainer tmpPredC;
ArmISA::VecPredRegContainer tmpPredC;
auto auxPOp1 = tmpPredC.as<SElement>();
for (int i = 0; i < eCount; ++i) {
auxPOp1[i] = POp1_xs[i];
}'''
else:
code += '''
TheISA::VecRegContainer tmpVecC;
ArmISA::VecRegContainer tmpVecC;
auto auxOp1 = tmpVecC.as<SElement>();
for (int i = 0; i < eCount; ++i) {
auxOp1[i] = AA64FpOp1_xs[i];
@@ -2636,7 +2636,7 @@ let {{
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
TheISA::VecRegContainer tmpVecC;
ArmISA::VecRegContainer tmpVecC;
auto auxOp1 = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
auxOp1[i] = AA64FpOp1_x[i];
@@ -2707,7 +2707,7 @@ let {{
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
TheISA::VecRegContainer tmpVecC;
ArmISA::VecRegContainer tmpVecC;
auto auxOp1 = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
auxOp1[i] = AA64FpOp1_x[i];
@@ -2736,7 +2736,7 @@ let {{
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
TheISA::VecRegContainer tmpVecC;
ArmISA::VecRegContainer tmpVecC;
auto auxDest = tmpVecC.as<Element>();
int firstelem = -1, lastelem = -2;
for (int i = 0; i < eCount; ++i) {
@@ -2799,7 +2799,7 @@ let {{
xc->tcBase());'''
if srcType == SrcRegType.Predicate:
code += '''
TheISA::VecPredRegContainer tmpPredC;
ArmISA::VecPredRegContainer tmpPredC;
auto auxPOp1 = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
uint8_t v = POp1_x.get_raw(i);
@@ -2808,7 +2808,7 @@ let {{
PDest_x[0] = 0;'''
else:
code += '''
TheISA::VecRegContainer tmpRegC;
ArmISA::VecRegContainer tmpRegC;
auto auxOp1 = tmpRegC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
auxOp1[i] = AA64FpOp1_x[i];
@@ -4464,7 +4464,7 @@ let {{
constexpr unsigned sz = sizeof(Element);
int s;
int part = %d;
TheISA::VecPredRegContainer tmpPredC;
ArmISA::VecPredRegContainer tmpPredC;
auto auxPDest = tmpPredC.as<uint8_t>();
for (unsigned i = 0; i < eCount / 2; i++) {
s = 2 * i + part;
@@ -4485,7 +4485,7 @@ let {{
trnIterCode = '''
int s;
int part = %d;
TheISA::VecRegContainer tmpVecC;
ArmISA::VecRegContainer tmpVecC;
auto auxDest = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount / 2; i++) {
s = 2 * i + part;
@@ -4681,7 +4681,7 @@ let {{
constexpr unsigned sz = sizeof(Element);
int s;
int part = %d;
TheISA::VecPredRegContainer tmpPredC;
ArmISA::VecPredRegContainer tmpPredC;
auto auxPDest = tmpPredC.as<uint8_t>();
for (unsigned i = 0; i < eCount; i++) {
s = 2 * i + part;
@@ -4705,7 +4705,7 @@ let {{
uzpIterCode = '''
int s;
int part = %d;
TheISA::VecRegContainer tmpVecC;
ArmISA::VecRegContainer tmpVecC;
auto auxDest = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; i++) {
s = 2 * i + part;
@@ -4766,7 +4766,7 @@ let {{
constexpr unsigned sz = sizeof(Element);
int s;
int part = %d;
TheISA::VecPredRegContainer tmpPredC;
ArmISA::VecPredRegContainer tmpPredC;
auto auxPDest = tmpPredC.as<uint8_t>();
for (unsigned i = 0; i < eCount / 2; i++) {
s = i + (part * (eCount / 2));
@@ -4787,7 +4787,7 @@ let {{
zipIterCode = '''
int s;
int part = %d;
TheISA::VecRegContainer tmpVecC;
ArmISA::VecRegContainer tmpVecC;
auto auxDest = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount / 2; i++) {
s = i + (part * (eCount / 2));

4
src/arch/arm/isa/operands.isa
View File

@@ -51,12 +51,12 @@ def operand_types {{
'tud' : 'std::array<uint64_t, 2>',
'sf' : 'float',
'df' : 'double',
'vc' : 'TheISA::VecRegContainer',
'vc' : 'ArmISA::VecRegContainer',
# For operations that are implemented as a template
'x' : 'TPElem',
'xs' : 'TPSElem',
'xd' : 'TPDElem',
'pc' : 'TheISA::VecPredRegContainer',
'pc' : 'ArmISA::VecPredRegContainer',
'pb' : 'uint8_t'
}};

2
src/arch/arm/tracers/tarmac_base.cc
View File

@@ -47,7 +47,7 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
using namespace TheISA;
using namespace ArmISA;
namespace Trace {

8
src/arch/arm/tracers/tarmac_base.hh
View File

@@ -85,7 +85,7 @@ class TarmacBaseRecord : public InstRecord
{
InstEntry() = default;
InstEntry(ThreadContext* thread,
TheISA::PCState pc,
ArmISA::PCState pc,
const StaticInstPtr staticInst,
bool predicate);
@@ -101,7 +101,7 @@ class TarmacBaseRecord : public InstRecord
struct RegEntry
{
RegEntry() = default;
RegEntry(TheISA::PCState pc);
RegEntry(ArmISA::PCState pc);
RegType type;
RegIndex index;
@@ -123,7 +123,7 @@ class TarmacBaseRecord : public InstRecord
public:
TarmacBaseRecord(Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst, TheISA::PCState _pc,
const StaticInstPtr _staticInst, ArmISA::PCState _pc,
const StaticInstPtr _macroStaticInst = NULL);
virtual void dump() = 0;
@@ -135,7 +135,7 @@ class TarmacBaseRecord : public InstRecord
* @param pc program counter (PCState) variable
* @return Instruction Set State for the given PCState
*/
static ISetState pcToISetState(TheISA::PCState pc);
static ISetState pcToISetState(ArmISA::PCState pc);
};

10
src/arch/arm/tracers/tarmac_parser.cc
View File

@@ -57,7 +57,7 @@
#include "sim/sim_exit.hh"
using namespace std;
using namespace TheISA;
using namespace ArmISA;
namespace Trace {
@@ -743,7 +743,7 @@ TarmacParserRecord::TarmacParserRecordEvent::description() const
void
TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst,
TheISA::PCState pc)
ArmISA::PCState pc)
{
ostream &outs = Trace::output();
outs << "\nMismatch between gem5 and TARMAC trace @ " << dec << curTick()
@@ -776,8 +776,8 @@ TarmacParserRecord::dump()
// By default TARMAC splits memory accesses into 4-byte chunks (see
// 'loadstore-display-width' option in TARMAC plugin)
uint32_t written_data = 0;
unsigned mem_flags = TheISA::TLB::MustBeOne | 3 |
TheISA::TLB::AllowUnaligned;
unsigned mem_flags = ArmISA::TLB::MustBeOne | 3 |
ArmISA::TLB::AllowUnaligned;
ISetState isetstate;
@@ -1051,7 +1051,7 @@ TarmacParserRecord::readMemNoEffect(Addr addr, uint8_t *data, unsigned size,
unsigned flags)
{
const RequestPtr &req = memReq;
TheISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
req->setVirt(0, addr, size, flags, thread->pcState().instAddr(),
Request::funcMasterId);

10
src/arch/arm/tracers/tarmac_parser.hh
View File

@@ -83,7 +83,7 @@ class TarmacParserRecord : public TarmacBaseRecord
/** Current instruction. */
const StaticInstPtr inst;
/** PC of the current instruction. */
TheISA::PCState pc;
ArmISA::PCState pc;
/** True if a mismatch has been detected for this instruction. */
bool mismatch;
/**
@@ -95,7 +95,7 @@ class TarmacParserRecord : public TarmacBaseRecord
TarmacParserRecordEvent(TarmacParser& _parent,
ThreadContext *_thread,
const StaticInstPtr _inst,
TheISA::PCState _pc,
ArmISA::PCState _pc,
bool _mismatch,
bool _mismatch_on_pc_or_opcode) :
parent(_parent), thread(_thread), inst(_inst), pc(_pc),
@@ -130,10 +130,10 @@ class TarmacParserRecord : public TarmacBaseRecord
* by gem5.
*/
static void printMismatchHeader(const StaticInstPtr inst,
TheISA::PCState pc);
ArmISA::PCState pc);
TarmacParserRecord(Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst, TheISA::PCState _pc,
const StaticInstPtr _staticInst, ArmISA::PCState _pc,
TarmacParser& _parent,
const StaticInstPtr _macroStaticInst = NULL);
@@ -241,7 +241,7 @@ class TarmacParser : public InstTracer
InstRecord *
getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst,
TheISA::PCState pc,
ArmISA::PCState pc,
const StaticInstPtr macroStaticInst = NULL)
{
if (!started && pc.pc() == startPc)

2
src/arch/arm/tracers/tarmac_record.hh
View File

@@ -178,7 +178,7 @@ class TarmacTracerRecord : public TarmacBaseRecord
public:
TarmacTracerRecord(Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst, TheISA::PCState _pc,
const StaticInstPtr _staticInst, ArmISA::PCState _pc,
TarmacTracer& _tracer,
const StaticInstPtr _macroStaticInst = NULL);

4
src/arch/arm/tracers/tarmac_record_v8.cc
View File

@@ -56,7 +56,7 @@ TarmacTracerRecordV8::TraceInstEntryV8::TraceInstEntryV8(
const auto thread = tarmCtx.thread;
// Evaluate physical address
TheISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
paddrValid = dtb->translateFunctional(thread, addr, paddr);
}
@@ -70,7 +70,7 @@ TarmacTracerRecordV8::TraceMemEntryV8::TraceMemEntryV8(
const auto thread = tarmCtx.thread;
// Evaluate physical address
TheISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
dtb->translateFunctional(thread, addr, paddr);
}

2
src/arch/arm/tracers/tarmac_record_v8.hh
View File

@@ -130,7 +130,7 @@ class TarmacTracerRecordV8 : public TarmacTracerRecord
public:
TarmacTracerRecordV8(Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst, TheISA::PCState _pc,
const StaticInstPtr _staticInst, ArmISA::PCState _pc,
TarmacTracer& _parent,
const StaticInstPtr _macroStaticInst = NULL)
: TarmacTracerRecord(_when, _thread, _staticInst, _pc,

2
src/arch/arm/tracers/tarmac_tracer.cc
View File

@@ -75,7 +75,7 @@ TarmacTracer::TarmacTracer(const Params *p)
InstRecord *
TarmacTracer::getInstRecord(Tick when, ThreadContext *tc,
const StaticInstPtr staticInst,
TheISA::PCState pc,
ArmISA::PCState pc,
const StaticInstPtr macroStaticInst)
{
// Check if we need to start tracing since we have passed the

6
src/arch/arm/tracers/tarmac_tracer.hh
View File

@@ -63,7 +63,7 @@ class TarmacContext
public:
TarmacContext(ThreadContext* _thread,
const StaticInstPtr _staticInst,
TheISA::PCState _pc)
ArmISA::PCState _pc)
: thread(_thread), staticInst(_staticInst), pc(_pc)
{}
@@ -72,7 +72,7 @@ class TarmacContext
public:
ThreadContext* thread;
const StaticInstPtr staticInst;
TheISA::PCState pc;
ArmISA::PCState pc;
};
/**
@@ -99,7 +99,7 @@ class TarmacTracer : public InstTracer
*/
InstRecord* getInstRecord(Tick when, ThreadContext *tc,
const StaticInstPtr staticInst,
TheISA::PCState pc,
ArmISA::PCState pc,
const StaticInstPtr macroStaticInst = NULL);
protected:

2
src/arch/mips/utility.cc
View File

@@ -268,7 +268,7 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest)
void
skipFunction(ThreadContext *tc)
{
TheISA::PCState newPC = tc->pcState();
PCState newPC = tc->pcState();
newPC.set(tc->readIntReg(ReturnAddressReg));
tc->pcState(newPC);
}

2
src/arch/power/stacktrace.hh
View File

@@ -57,8 +57,6 @@ class ProcessInfo
class StackTrace
{
protected:
typedef TheISA::MachInst MachInst;
private:
ThreadContext *tc;
std::vector<Addr> stack;

2
src/arch/riscv/stacktrace.hh
View File

@@ -57,8 +57,6 @@ class ProcessInfo
class StackTrace
{
protected:
typedef TheISA::MachInst MachInst;
private:
ThreadContext *tc;
std::vector<Addr> stack;

2
src/arch/sparc/utility.cc
View File

@@ -248,7 +248,7 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
void
skipFunction(ThreadContext *tc)
{
TheISA::PCState newPC = tc->pcState();
PCState newPC = tc->pcState();
newPC.set(tc->readIntReg(ReturnAddressReg));
tc->pcState(newPC);
}

2
src/arch/x86/process.cc
View File

@@ -150,7 +150,7 @@ X86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile,
void
I386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault)
{
TheISA::PCState pc = tc->pcState();
PCState pc = tc->pcState();
Addr eip = pc.pc();
if (eip >= vsyscallPage.base &&
eip < vsyscallPage.base + vsyscallPage.size) {