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arch-arm: Remove un-needed hyp flag in TLBI operations

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The hyp flag was probably a legacy pre-v8 flag distinguishing
invalidation targeting PL2 translation regime (hyp mode).
Since the introduction of target_el parameter, hyp boolean is not needed
anymore.  The patch works by setting the hyp flag in the flush* methods
in the TLB automatically by checking if target_el == EL2.

Change-Id: I798009e09ff24a383dea871e348188bae2685e8e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18389
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-04-10 15:45:30 +01:00
parent 670d080aa1
commit e8d0b755ea
5 changed files with 46 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
src/arch/arm/isa.cc
View File

@@ -1191,7 +1191,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
mbits(newVal, 31,12), false);
mbits(newVal, 31,12));
tlbiOp(tc);
return;
@@ -1204,7 +1204,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
mbits(newVal, 31,12), false);
mbits(newVal, 31,12));
tlbiOp.broadcast(tc);
return;
@@ -1220,7 +1220,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
mbits(newVal, 31,12), true);
mbits(newVal, 31,12));
tlbiOp(tc);
return;
@@ -1233,7 +1233,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
mbits(newVal, 31,12), true);
mbits(newVal, 31,12));
tlbiOp.broadcast(tc);
return;
@@ -1329,7 +1329,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
{
assert32(tc);
TLBIALLN tlbiOp(EL1, false);
TLBIALLN tlbiOp(EL1);
tlbiOp(tc);
return;
}
@@ -1338,7 +1338,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
{
assert32(tc);
TLBIALLN tlbiOp(EL1, false);
TLBIALLN tlbiOp(EL1);
tlbiOp.broadcast(tc);
return;
}
@@ -1347,7 +1347,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
{
assert32(tc);
TLBIALLN tlbiOp(EL2, true);
TLBIALLN tlbiOp(EL2);
tlbiOp(tc);
return;
}
@@ -1356,7 +1356,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
{
assert32(tc);
TLBIALLN tlbiOp(EL2, true);
TLBIALLN tlbiOp(EL2);
tlbiOp.broadcast(tc);
return;
}
@@ -1538,7 +1538,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
static_cast<Addr>(bits(newVal, 43, 0)) << 12);
tlbiOp(tc);
return;
@@ -1551,7 +1551,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
static_cast<Addr>(bits(newVal, 43, 0)) << 12);
tlbiOp.broadcast(tc);
return;

21
src/arch/arm/tlb.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2013, 2016-2018 ARM Limited
* Copyright (c) 2010-2013, 2016-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -265,8 +265,10 @@ TLB::flushAllSecurity(bool secure_lookup, uint8_t target_el, bool ignore_el)
}
void
TLB::flushAllNs(bool hyp, uint8_t target_el, bool ignore_el)
TLB::flushAllNs(uint8_t target_el, bool ignore_el)
{
bool hyp = target_el == EL2;
DPRINTF(TLB, "Flushing all NS TLB entries (%s lookup)\n",
(hyp ? "hyp" : "non-hyp"));
int x = 0;
@@ -297,7 +299,7 @@ TLB::flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup, uint8_t target_el)
DPRINTF(TLB, "Flushing TLB entries with mva: %#x, asid: %#x "
"(%s lookup)\n", mva, asn, (secure_lookup ?
"secure" : "non-secure"));
_flushMva(mva, asn, secure_lookup, false, false, target_el);
_flushMva(mva, asn, secure_lookup, false, target_el);
flushTlbMvaAsid++;
}
@@ -326,21 +328,24 @@ TLB::flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el)
}
void
TLB::flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el)
TLB::flushMva(Addr mva, bool secure_lookup, uint8_t target_el)
{
DPRINTF(TLB, "Flushing TLB entries with mva: %#x (%s lookup)\n", mva,
(secure_lookup ? "secure" : "non-secure"));
_flushMva(mva, 0xbeef, secure_lookup, hyp, true, target_el);
_flushMva(mva, 0xbeef, secure_lookup, true, target_el);
flushTlbMva++;
}
void
TLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool hyp,
TLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup,
bool ignore_asn, uint8_t target_el)
{
TlbEntry *te;
// D5.7.2: Sign-extend address to 64 bits
mva = sext<56>(mva);
bool hyp = target_el == EL2;
te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn,
target_el);
while (te != NULL) {
@@ -355,10 +360,10 @@ TLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool hyp,
}
void
TLB::flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el)
TLB::flushIpaVmid(Addr ipa, bool secure_lookup, uint8_t target_el)
{
assert(!isStage2);
stage2Tlb->_flushMva(ipa, 0xbeef, secure_lookup, hyp, true, target_el);
stage2Tlb->_flushMva(ipa, 0xbeef, secure_lookup, true, target_el);
}
bool

14
src/arch/arm/tlb.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2013, 2016, 2018 ARM Limited
* Copyright (c) 2010-2013, 2016, 2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -254,9 +254,8 @@ class TLB : public BaseTLB
/** Remove all entries in the non secure world, depending on whether they
* were allocated in hyp mode or not
* @param hyp if the opperation affects hyp mode
*/
void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
void flushAllNs(uint8_t target_el, bool ignore_el = false);
/** Reset the entire TLB. Used for CPU switching to prevent stale
@@ -285,18 +284,16 @@ class TLB : public BaseTLB
/** Remove all entries that match the va regardless of asn
* @param mva address to flush from cache
* @param secure_lookup if the operation affects the secure world
* @param hyp if the operation affects hyp mode
*/
void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
void flushMva(Addr mva, bool secure_lookup, uint8_t target_el);
/**
* Invalidate all entries in the stage 2 TLB that match the given ipa
* and the current VMID
* @param ipa the address to invalidate
* @param secure_lookup if the operation affects the secure world
* @param hyp if the operation affects hyp mode
*/
void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el);
void flushIpaVmid(Addr ipa, bool secure_lookup, uint8_t target_el);
Fault trickBoxCheck(const RequestPtr &req, Mode mode,
TlbEntry::DomainType domain);
@@ -450,11 +447,10 @@ private:
* @param mva virtual address to flush
* @param asn contextid/asn to flush on match
* @param secure_lookup if the operation affects the secure world
* @param hyp if the operation affects hyp mode
* @param ignore_asn if the flush should ignore the asn
*/
void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
bool hyp, bool ignore_asn, uint8_t target_el);
bool ignore_asn, uint8_t target_el);
bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);

26
src/arch/arm/tlbi_op.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018 ARM Limited
* Copyright (c) 2018-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -99,26 +99,26 @@ DTLBIASID::operator()(ThreadContext* tc)
void
TLBIALLN::operator()(ThreadContext* tc)
{
getITBPtr(tc)->flushAllNs(hyp, targetEL);
getDTBPtr(tc)->flushAllNs(hyp, targetEL);
getITBPtr(tc)->flushAllNs(targetEL);
getDTBPtr(tc)->flushAllNs(targetEL);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
getITBPtr(checker)->flushAllNs(hyp, targetEL);
getDTBPtr(checker)->flushAllNs(hyp, targetEL);
getITBPtr(checker)->flushAllNs(targetEL);
getDTBPtr(checker)->flushAllNs(targetEL);
}
}
void
TLBIMVAA::operator()(ThreadContext* tc)
{
getITBPtr(tc)->flushMva(addr, secureLookup, hyp, targetEL);
getDTBPtr(tc)->flushMva(addr, secureLookup, hyp, targetEL);
getITBPtr(tc)->flushMva(addr, secureLookup, targetEL);
getDTBPtr(tc)->flushMva(addr, secureLookup, targetEL);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
getITBPtr(checker)->flushMva(addr, secureLookup, hyp, targetEL);
getDTBPtr(checker)->flushMva(addr, secureLookup, hyp, targetEL);
getITBPtr(checker)->flushMva(addr, secureLookup, targetEL);
getDTBPtr(checker)->flushMva(addr, secureLookup, targetEL);
}
}
@@ -157,16 +157,16 @@ void
TLBIIPA::operator()(ThreadContext* tc)
{
getITBPtr(tc)->flushIpaVmid(addr,
secureLookup, false, targetEL);
secureLookup, targetEL);
getDTBPtr(tc)->flushIpaVmid(addr,
secureLookup, false, targetEL);
secureLookup, targetEL);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
getITBPtr(checker)->flushIpaVmid(addr,
secureLookup, false, targetEL);
secureLookup, targetEL);
getDTBPtr(checker)->flushIpaVmid(addr,
secureLookup, false, targetEL);
secureLookup, targetEL);
}
}

14
src/arch/arm/tlbi_op.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018 ARM Limited
* Copyright (c) 2018-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -169,14 +169,11 @@ class DTLBIASID : public TLBIOp
class TLBIALLN : public TLBIOp
{
public:
TLBIALLN(ExceptionLevel _targetEL, bool _hyp)
: TLBIOp(_targetEL, false), hyp(_hyp)
TLBIALLN(ExceptionLevel _targetEL)
: TLBIOp(_targetEL, false)
{}
void operator()(ThreadContext* tc) override;
protected:
bool hyp;
};
/** TLB Invalidate by VA, All ASID */
@@ -184,15 +181,14 @@ class TLBIMVAA : public TLBIOp
{
public:
TLBIMVAA(ExceptionLevel _targetEL, bool _secure,
Addr _addr, bool _hyp)
: TLBIOp(_targetEL, _secure), addr(_addr), hyp(_hyp)
Addr _addr)
: TLBIOp(_targetEL, _secure), addr(_addr)
{}
void operator()(ThreadContext* tc) override;
protected:
Addr addr;
bool hyp;
};
/** TLB Invalidate by VA */