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arch-arm: Correct target EL field in TLBI operations

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Some TLB Invalidation operations affecting the EL2 translation regime
were marked as targeting EL1 instead of EL2

Change-Id: I77821eec7a409e9df6a6814855f9a375832ffe74
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18388
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-04-10 14:26:47 +01:00
parent 40018b14a6
commit 670d080aa1
1 changed files with 4 additions and 4 deletions
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8
src/arch/arm/isa.cc
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@@ -1219,7 +1219,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
assert32(tc);
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
mbits(newVal, 31,12), true);
tlbiOp(tc);
@@ -1232,7 +1232,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
assert32(tc);
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
mbits(newVal, 31,12), true);
tlbiOp.broadcast(tc);
@@ -1347,7 +1347,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
{
assert32(tc);
TLBIALLN tlbiOp(EL1, true);
TLBIALLN tlbiOp(EL2, true);
tlbiOp(tc);
return;
}
@@ -1356,7 +1356,7 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
{
assert32(tc);
TLBIALLN tlbiOp(EL1, true);
TLBIALLN tlbiOp(EL2, true);
tlbiOp.broadcast(tc);
return;
}