Commit Graph

5014 Commits

Author SHA1 Message Date
Alistair Delva
cb7799648b arch-arm: Add support for initrd/initramfs
Add initrd_filename and initrd_addr parameters to specify that an
initrd/initramfs should be loaded into memory from a file, just like the
DTB blob. The user must specify the initrd file, and they can specify
the initrd load address as well. However, in practice, it's expected
that the dev/machine backend will derive the initrd load address from
the dtb load address, which is how a bootloader would typically do it.

Change-Id: I6378927c2984b7ccdd1471486dd7803500ef5883
Signed-off-by: Alistair Delva <adelva@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54184
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-01-05 21:38:34 +00:00
Eric Ye
f894de5486 scons: Try to fix build dependency bug when generating fastmodels
Bug: 201084562
Change-Id: I33cc9e09b1ce46f80864d75f088a2534949e55e1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55043
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-01-05 15:29:32 +00:00
Luming Wang
1f155ffd90 arch-riscv,sim-se: Complements the system calls on RISC-V
There are many SE mode system calls that are implemented
in src/sim/syscall_emul.cc or src/sim/syscall_emul.hh.
And they work well under X86 and ARM platforms. However,
they are not supported in se_workload.cc under the RISC-V
platform. This patch adds support for all the system calls
already implemented in syscall_emul.hh/cc to the RISC-V
platform (in arch/riscv/linux/se_workload.cc).

Change-Id: Ia47c3c113767b50412b1c8ade3c1047c894376cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54803
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2022-01-05 03:25:58 +00:00
Bobby R. Bruce
065a7dbf1b misc: Merge branch release-staging-v21-2 into develop
Change-Id: I8200ac51c20117f63b51d555fa2f12e5dd35f22e
2021-12-26 23:59:41 -08:00
Cui Jin
2194aea053 arch-riscv: rvc instruction is mistaken as branch
Fetch in O3CPU mistakes the normal non-branching compressed
instructions, and regards it as a branch. This issue interrupts
the consecutive instruction stream, thus affecting performance
of cpu front-end.
This fix sets the compressed for PCState during decoding.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1137

Change-Id: I7607d563bba8a08869e104877fc3c11c94cbe904
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54644
Reviewed-by: Jin Cui <cuijinbird@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-22 23:51:50 +00:00
Kyle Roarty
f9deeea427 arch-gcn3,arch-vega: Select proper data on misaligned access
req1->getSize() returns the size in bytes, but because we're using it
in an array index, we need to scale it by the size of the data type.

This ensures we give the second request the proper data.

Change-Id: I578665406762d5d0c95f2ea8297c362e1cc0620b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54503
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
2021-12-20 18:28:08 +00:00
Gabe Black
c154888b2a arch,sim-se: Handle syscall retry/suppression in the syscall desc.
Rather than make each ISA include boilerplate to ignore a
SyscallReturn's value when it's marked as suppressed or needing a retry,
put that code into the SyscallDesc::doSyscall method instead.

That has two benefits. First, it removes a decent amount of code
duplication which is nice from a maintenance perspective. Second, it
puts the SyscallDesc in charge of figuring out what to do once a system
call implementation finishes. That will let it schedule a retry of the
system call for instance, without worrying about what the ISA is doing
with the SyscallReturn behind its back.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1123

Change-Id: I76760cba75fd23e6e3357f6169c0140bee3f01b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54204
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-17 05:45:26 +00:00
Yu-hsin Wang
110e22439f arch-arm: gdb support Thumb-2 ISA
From the document*1, we should allow 2,3,4 in kind check function for
supporting all kinds of ARM breakpoint.

1. https://sourceware.org/gdb/current/onlinedocs/gdb/ARM-Breakpoint-Kinds.html

Change-Id: I82bcb88cfe6e80e7f17cd6bb68a26a45ace7b174
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54124
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-16 13:26:45 +00:00
Yu-hsin Wang
46957f4337 base: Correct checkBpLen naming with checkBpKind
In gdb document*1, the second parameter of checkpoint command(Z0, Z1) is
named after kind. Although underlying implementation probably considers
it as length*2, it's still good to follow the name described in gdb
document for avoiding any confusion.

Refs:
1. https://sourceware.org/gdb/onlinedocs/gdb/Packets.html
2. https://github.com/bminor/binutils-gdb/blob/master/gdb/arch-utils.h#L41

Change-Id: Ib4b585613b8018970b16355f96cdff2ce9d5bae6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54123
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-12-16 13:26:39 +00:00
Giacomo Travaglini
a923674d62 arch-arm: Do not squash table walks if translation is partial
As partial translations have been introduced we cannot just
rely on checking if there is a valid translation when looking
for translations to squash.
The translation has to be complete as well.

This is fixing realview-o3-checker regression

Change-Id: I1ad42bd6172207a72f53b7a843c323c0eea88f06
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54043
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
(cherry picked from commit ec891adca9)
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54103
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2021-12-14 09:43:41 +00:00
Gabe Black
2be95c4470 arch,sim-se: Handle syscall retry/suppression in the syscall desc.
Rather than make each ISA include boilerplate to ignore a
SyscallReturn's value when it's marked as suppressed or needing a retry,
put that code into the SyscallDesc::doSyscall method instead.

That has two benefits. First, it removes a decent amount of code
duplication which is nice from a maintenance perspective. Second, it
puts the SyscallDesc in charge of figuring out what to do once a system
call implementation finishes. That will let it schedule a retry of the
system call for instance, without worrying about what the ISA is doing
with the SyscallReturn behind its back.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1123

Change-Id: I3732a98c8e0d0b2b94d61313960aa0782c0b971f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54023
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-12-13 20:31:51 +00:00
Giacomo Travaglini
ec891adca9 arch-arm: Do not squash table walks if translation is partial
As partial translations have been introduced we cannot just
rely on checking if there is a valid translation when looking
for translations to squash.
The translation has to be complete as well.

This is fixing realview-o3-checker regression

Change-Id: I1ad42bd6172207a72f53b7a843c323c0eea88f06
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54043
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-13 09:22:01 +00:00
Giacomo Travaglini
fcb544d569 arch-arm: Allow the L2 unified TLB to store partial translations
We are allowing the L2 TLB to store partial translations from the
second level of lookup

JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: I1286c14a256470c2075fe5533930617139d4d087
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52126
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-12 05:04:24 +00:00
Giacomo Travaglini
6ea9a7fe73 arch-arm: Allowing table descriptor to be inserted in TLB
This patch is modifying both TableWalker and MMU to effectively
store/use partial translations

* TableWalker changes: If there is a TLB supporting partial
translations (implemented with previous patch), the TableWalker will
craft partial entries and forward them to the TLB as walks are performed

* MMU changes: We now instruct the table walker to start a page
table traversal even if we hit in the TLB, if the matching entry
holds a partial translation

JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: Id20aaf4ea02960d50d8345f3e174c698af21ad1c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52125
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-12 05:04:24 +00:00
Giacomo Travaglini
49cb833ee6 arch-arm: Allow TLB to be used as a WalkCache
This patch allows partial translation entries (intermediate PAs obtained
from a table walk) to be stored in an ArmTLB. This effectively means
reserving a fraction of the TLB entries to cache table walks

JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: Id0efb7d75dd017366c4c3b74de7b57355a53a01a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52124
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-12 05:04:24 +00:00
Gabe Black
8452e7bf19 arch,sim-se: Update the PC before emulating a system call.
For most system calls, it doesn't matter if the PC is advanced to the
instruction after the system call instruction before or after the system
call itself is invoked, because the system call itself doesn't interact
with it.

For some system calls however, specifically "clone" and "execve",
advancing the PC *after* the system call complicates things, because it
means the system call needs to set the PC to something that will equal
the desired value only *after* it's advanced.

By setting the PC *before* the system call, the system call can set the
PC to whatever it needs to. This means the new cloned context doesn't
need to advance the PC because it's already advanced, and execve doesn't
need to set NPC, it can leave the PC set to the correct value from the
entry point set during Process initialization.

Change-Id: I830607c2e9adcc22e738178fd3663417512e2e56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53983
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Kyle Roarty <kyleroarty1716@gmail.com>
2021-12-12 00:29:53 +00:00
Matthew Poremba
9313294efe misc: Remove AMD license addition
Remove the line "For use for simulation and test purposes only" in files
were AMD is the only copyright holder listed in the header. This happens
to be the case for all files where this line exists, removing it
completely from gem5.

Change-Id: I623f266b002f564301b28774f49081099cfc60fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53943
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 04:00:56 +00:00
Matthew Poremba
0ae1a9d109 arch-vega: Implement S_SLEEP
This is merely copied from arch-gcn3.

Change-Id: Ibd2bda37fe9adc083a35efab0f59617d386019b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53883
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Matthew Poremba
23aec13f07 arch-vega: Implement V_AND_OR_B32
Change-Id: I8daeb8de2db5996e132cf7ed729f02c3c94a6862
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53868
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Matthew Poremba
f1e3fa7a3e arch-vega: Implement V_ADD3_U32
Change-Id: I4d01265f946e289cbff56090c2dd193ea66d5c70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53867
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Matthew Poremba
2abc51e810 arch-vega: Impelemnt V_ADD_LSHL_U32
Change-Id: Ia4e465ef2534fe28dc846f728b2e1da3dfe4f7d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53866
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Matthew Poremba
04d025806d arch-vega: Implement V_LSHL_ADD_U32
Change-Id: I986f82e8c6c02b0d62e55fbaed1c3f9e5b2b4a43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53865
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Matthew Poremba
19788d3b56 arch-vega: Implement V_LSHL_OR_B32
Change-Id: I237410e05df9a96323a6ceb7d09ae2a2a8608f16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53864
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Matthew Poremba
b5d8d9ddcc arch-vega: Implement V_OR3_B32
Change-Id: Id6c074033b08058b739e056f06b40ee5735f8f00
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53863
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-11 03:59:19 +00:00
Giacomo Travaglini
ef34cd0a00 arch-arm: Add partial param to TlbEntry
The boolean will flag a partial translation

JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: Ia27e321cd5c4b062cafcfd0dc39a208a4d5e3247
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52123
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-10 16:09:09 +00:00
Giacomo Travaglini
db05eb9d89 arch-arm: Use ArmRelease in MMU and TableWalker
Change-Id: I210c73e0e66390f702dad6e7d737c8271b119091
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51408
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-09 19:21:03 +00:00
Matthew Poremba
c028af111a arch-gcn3,gpu-compute: Move TLB to common folder in amdgpu
This TLB is more of an "APU" TLB than anything GCN3 specific. It can be
used with either GCN3 or Vega. With this change, VEGA_X86 builds and one
can run binaries with Vega ISA code using the same steps as GCN3 but
building the Vega ISA instead.

Change-Id: I0c92bcd0379a18628dc05cb5af070bdc7e692c7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53803
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-09 17:26:15 +00:00
Matthew Poremba
85eaf9c799 arch-gcn3: Delete extraneous registers header
This file is a duplicate of arch/amdgpu/gcn3/gpu_registers.hh and is in
the wrong location. It should be removed to avoid mistakenly editing the
wrong file.

Change-Id: Ie96e22fe8f78fda954af788b472ec2df4782e4a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53743
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-12-08 14:59:53 +00:00
Gabe Black
1c233ee9d2 scons: Add sim_object and enums arguments to SimObject().
This will explicitly declare what SimObject and Enum types need to be set
up in C++, which will make importing all the SimObject modules during
the setup phase of SCons uneccessary.

Change-Id: Id2d7603daf33b236ceaa0789e2f089f589d34e62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49406
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-08 08:01:23 +00:00
Yu-hsin Wang
60e55ecef8 fastmodel: CortexR52 implements setResetAddr interface
Change-Id: I45da1c1538430061cc89f666cb02aa5fe77abcba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53328
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
2021-12-08 03:12:36 +00:00
Yu-hsin Wang
0e48a05ed1 fastmodel: CortexA76 implements setResetAddr interface
Change-Id: I3612a62e2145d3442f01a69b21954fc00dd5ade9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53327
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
2021-12-08 03:12:36 +00:00
Yu-hsin Wang
869d225e51 fastmodel: add setResetAddr interface
setResetAddr interface allows us to change the reset addr of fastmodel
cores. This will enable us to simulate hard reset or even complicated
boot sequence.

Change-Id: I0de828a4cd693119c0b44c74866efc1fffa81ace
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53326
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-08 03:12:36 +00:00
Gabe Black
7bd668217b arch-x86: Hook up the newfstatat system call for 64 bit Linux.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1117

Change-Id: I711fc7d7009621bb317981293725416ae74d1d3d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53206
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2021-12-07 22:58:40 +00:00
Gabe Black
a8e9258f99 arch-x86: Hook up system calls for 64 bit processes.
These system calls already exist, they just weren't hooked up yet.

Change-Id: I5c2c66d34d0286aafe686e6511948ed4a6719672
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53203
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2021-12-07 22:58:40 +00:00
Giacomo Travaglini
664fdd747a arch-arm, dev-arm: Add currEL function to the ISA class
This utility is strictly ISA related. We are still keeping the
version accepting the TC as an argument; this is just
wrapping the ISA call.

In this way we are simplifying life for ISA devices, which have
a reference to the ISA object rather than a reference to the TC

Change-Id: Icb286d174538b50962d31aa3f6e836b3c791dc1c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53624
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-07 18:58:49 +00:00
Giacomo Travaglini
2d8996a3eb arch-arm: Remove currOpMode utility function
This was used by the currEL function only. We are progressively
removing any interface referring to Armv7 concepts

Change-Id: I1d97b392d063e85562b9234c094b1f2166e75ac9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53623
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-07 18:58:49 +00:00
Giacomo Travaglini
adaab745a3 arch-arm, dev-arm: Move inSecureState helper to ISA class
The helper function should be really part of the Arm ISA class

Change-Id: Ida0393a12426c8973a9b8171ec2922c2dcec9f5a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53268
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-07 18:58:49 +00:00
Jason Lowe-Power
883b8fe826 arch-arm,arch-sparc: Remove legacy stat for faults
This is a legacy stat that was not easy to tie to a Stats::Group.

In ARM, this stat wasn't actually counting all faults, it was only
counting the faults that occured in 32-bit mode, so it's probably safe
to remove the stat (it was wrong anyway). For SPARC, it's also unlikely
anyone is depending on this stat for their research.

Change-Id: Ic6c60526ea51467627535d732258c50ce0d2c03b
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52504
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-07 15:03:38 +00:00
Gabe Black
35362d15f5 arch: Delete the decoder.hh switching header file.
Change-Id: I9340aa9fa87bcb03c27cb7107b6697ad96060dbe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52082
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-06 03:09:22 +00:00
Gabe Black
50732981ba cpu: Stop including arch/decoder.hh.
Stop including arch/decoder.hh, and fix up transitive includes.

Change-Id: I9ef2efd0ab427e17bea4382b89a097c17e619332
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52081
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-06 03:09:22 +00:00
Gabe Black
25d36c81c9 arch,cpu: Turn the Decoder objects into SimObjects.
Change-Id: I85839880db588b3b92064b8fcbf053c1811a1fdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52080
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-06 03:09:22 +00:00
Gabe Black
3e766837b0 arch,cpu: Stop using TheISA::Decoder in most places.
The only places that still use that indirection are where the decoder
itself is instantiated with "new".

Also, add an "as" method which makes casting to an ISA specific decoder
type easier and less error prone.

Change-Id: Ib4a9cce7f96da2a9a8fe19113628694904893b17
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52079
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-06 03:09:22 +00:00
Gabe Black
3d52a0ea97 arch: Make the decoder decode() method virtual.
Change-Id: I60f0c4ffbd63069caaee190a78f007df79b61808
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52078
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-06 03:09:22 +00:00
Gabe Black
ce60dc8d3a arch: Make the decoder moreBytes method virtual.
Change-Id: I9135508916de91172ec9649d59d80574ac2aaf16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52077
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-12-06 03:09:22 +00:00
Gabe Black
792745f4f0 arch: Make the decoder takeOverFrom method virtual.
This is only implemented for x86. It's called very rarely, and so
virtual function overhead is practically irrelevant.

Change-Id: Ib6e05a903df95b801164e44d1662e130419fdbd8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52076
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-12-06 03:09:22 +00:00
Gabe Black
b65272e7f1 arch: Remove "process()" from the Decoder interface.
This method was only ever an implementation detail on ARM and x86, the
only places it actually did anything. Remove it from the other decoders,
and also make it protected on x86 to remove confusion.

Change-Id: I3a719648039c1edfbc2bd044f0a21c8983b249f5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52075
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-03 03:24:44 +00:00
Gabe Black
81fa62fc91 arch: Make the decoder reset() method virtual.
This is called very infrequently, and so it's virtual overhead is
practically irrelevant.

Change-Id: If92cd96f75234c65c4cdffe392c32cfdd9b0c8cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52074
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-03 03:24:44 +00:00
Gabe Black
5e7c964158 arch: Promote outOfBytes/needMoreBytes to the InstDecoder class.
Change-Id: Ie8f31e424081f002e3d74edd1685b4a977c545c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52073
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-03 03:24:44 +00:00
Gabe Black
29950b81ce arch: Promote instReady to the base InstDecoder class.
Move the instDone flag, and the instReady function which was
consistently implemented just to return it, to the base InstDecoder
class. This flag can still be accessed easily from the subclasses, but
now it can be retrieved with just an InstDecoder pointer without a
virtual function call.

Change-Id: I8c662aa01da8fe33ffe679071c701e0aadc1a795
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52072
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-03 03:24:44 +00:00
Gabe Black
21d7ae9508 arch: Implement StaticInst::advancePC(ThreadContext *) for the ISAs.
Change-Id: Icc0332eca55c38f80964e7f898ccfa35da64fdf9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52070
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-03 03:05:41 +00:00