Commit Graph

5239 Commits

Author SHA1 Message Date
Gabe Black
caffb4e1ff arch: Detect and convert zero registers to InvalidRegClass.
Change-Id: Ic5e070d303bf05ed1640b441e498d879764b8778
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49745
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-06-07 18:26:22 +00:00
Gabe Black
8d11bc31b5 arch-arm: Fix dangling pointer to unnamed temporary in nativetrace.cc.
Name the temporary.

Change-Id: I51d0eaa4a6759c3f288b4215db880af6135e9107
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60409
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-06-07 06:37:04 +00:00
Hoa Nguyen
373cc39a92 arch-arm: Improve error message when KVM failed to be initialized
Change-Id: If7f87cbd6c4e01134b17875e7c69f6147a5ed1f6
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60312
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2022-06-06 18:17:37 +00:00
Hoa Nguyen
bf71a17982 arch-arm: Add several 64-bit syscalls name to se_workload.cc
The names are gathered from [1].

This change also makes syscall 293 (rseq) does nothing
instead of raising an error.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/include/uapi/asm-generic/unistd.h?h=v5.15.44.

Change-Id: Ie0a7221db1cc308316fc0a500c454a23bf6029fd
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60229
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-06-01 18:31:14 +00:00
Hoa Nguyen
96870d4713 arch-riscv: Fix compilation error due to getdents* syscalls
In src/sim/syscall_emul.*, getdents and getdents64 are guarded
by #ifdefs. Similar #ifdefs should be in se_workload.cc for each
arch.

Change-Id: Ie636a739235711c3e6d8256fd7929b7d8b4ec953
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60189
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-06-01 18:31:14 +00:00
ksco
53009f9e69 arch-riscv: Add Zfh extension
This commit adds RISC-V Zfh 1.0 (half-precision IEEE 754 binary16 floating
point) extension to gem5. Include the following commands:

* FLH / FSH
* FMADD.H / FMSUB.H / FNMSUB.H / FNMADD.H
* FADD.H / FSUB.H / FMUL.H / FDIV.H
* FSQRT.H
* FSGNJ.H / FSGNJN.H / FSGNJX.H
* FMIN.H / FMAX.H
* FCVT.S.H / FCVT.H.S
* FCVT.D.H / FCVT.H.D
* FCVT.W.H / FCVT.H.W
* FCVT.WU.H / FCVT.H.WU
* FMV.X.H / FMV.H.X
* FEQ.H / FLT.H / FLE.H
* FCLASS.H
* FCVT.L.H / FCVT.H.L
* FCVT.LU.H / FCVT.H.LU

Change-Id: Id7870fdfa1aa8b840706c3ba2cab8eeaf008880f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60029
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-27 01:22:31 +00:00
Bobby R. Bruce
ed6c57e4ab tests,arch-arm: Add guards for ARM-specific test
The nightly tests, https://jenkins.gem5.org/job/nightly/219/, were
failing with the following error when running build/NULL/unittests.opt:

```
[ENUMDECL] m5.objects.ArmSystem, ArmExtension -> NULL/enums/ArmExtension.hh
terminate called after throwing an instance of 'pybind11::error_already_set'
  what():  ModuleNotFoundError: No module named 'm5.objects.ArmSystem'
At:
  <frozen importlib._bootstrap>(973): _find_and_load_unlocked
  <frozen importlib._bootstrap>(991): _find_and_load
  <frozen importlib._bootstrap>(1014): _gcd_import
  /usr/lib/python3.8/importlib/__init__.py(127): import_module
  build_tools/enum_hh.py(58): <module>
Aborted (core dumped)
scons: *** [build/NULL/enums/ArmExtension.hh] Error 134
```

The reason for this is the 'aapcs64.test' now transitively includes the
'ArmExtension' enum via this commit:
https://gem5-review.googlesource.com/c/public/gem5/+/59471.

As this test now only works with the ARM ISA, a guard has been included.
As noted in the comment, GTest does not have the 'tags' parameter so the
'TARGET_ISA' environment variable was used. This will need updated when
the multi-isa code is incorporated.

Change-Id: I2793094bf7c813afd97933750332fa3f3b7bd8dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59569
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-05-11 19:27:33 +00:00
Giacomo Travaglini
1455ac0e0c arch-arm: Turn on EL2/EL3 support by default in ArmSystem
In order to turn them off a user needs to explicitly do so
by providing a different ArmRelease objec

Change-Id: I227cee80c5517cdd50cf07c62d9a131ce261310f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51011
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-11 13:00:42 +00:00
Gabe Black
67f1ec7f5b fastmodel: Make ArmFastModelComponent-s take a tags parameter.
ArmFastModelComponents must *minimally* be guarded by "arm fastmodel"
tags, but may actually be covered by a more specific tag which is a
subset of "arm fastmodel", for instance if they are controlled by a
kconfig variable and may or may not be included in "gem5 lib"
independently of other sources which are part of "arm fastmodel".

The contents set up by ArmFastModelComponent are already guarded by a
fixed tag, so this change just needs to plumb through the tag as
specified when the ArmFastModelComponent is created instead.

Change-Id: I619c31107acda378a5439718e32938843f024e74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59473
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-05-09 20:05:32 +00:00
Giacomo Travaglini
fd250dbed3 arch-arm: Consolidate Arm FEAT check into single hasExtension
There's no need to have a per extension helper function now
that we rely on ArmExtension objects

We are therefore removing:

* HavePACExt
* HaveLVA
* HaveSecureEL2Ext
* HaveVirtHostExt

Change-Id: I2094c1eb6310506787e5628aa62d0b14e917ab5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59471
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-09 16:45:58 +00:00
Giacomo Travaglini
6412be29f4 arch-arm: Check implemented features through the release object
This is faster than going through the ISA and reading the corresponding
ID register value

Change-Id: Iec247167f3b99dcabf2908fceb0c2365c37ba017
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59470
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2022-05-09 16:45:58 +00:00
Giacomo Travaglini
20e1ade7ed arch-arm: Do not read SCR on the critical path
Change-Id: I0318563382b3c910c599f9fa16ad29553129c537
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59469
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-09 16:45:58 +00:00
Angie Lee
a8e8d64e5d fastmodel: Fix an index parsing bug on PL330::gem5_getPort
Change-Id: I2cf1abb0eb21c6bd65f81628be52650ef9250fbb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59369
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-09 08:47:45 +00:00
Giacomo Travaglini
7580e8d53d arch-arm: Memoize computeAddrTop in the MMU code
Profiling gem5 has indicated computeAddrTop as one of the main
contributors in AArch64 simulation time

The utility function gets used in the critical path of gem5, which is
the memory translation subsystem. The function is supposed to compute a
rather trivial task: identifying the "real" most significant bit of a
virtual address.

This turns out to be quite expensive. Why?

The main issue is the AArch32/AArch64 check, which uses the ELIs32
helper. This performs a sequential read of several MiscReg
values until it confirms that an EL is indeed using AArch32 (or
AArch64).

This is functionally accurate but it is too expensive for the critical
path of a program.

This patch is addressing the issue by adding a Memoizer object for the
computeAddrTop function to the CachedState data structure, which is
already holding cached system register values for performance reasons.
Whenever we need to invalidate those sys reg values because of a change
in the translation system, we also flush/invalidate the memoizer cache

Change-Id: If42e945c650c293ace304fb4c35e709783bb82d4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59151
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-05-04 14:04:56 +00:00
Hoa Nguyen
46266596ff arch-arm,cpu: Move KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 check to Kvm
This change [1] requires performing KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 check.
However, checkExtension() is only available within the Kvm class and
the KvmVM class.

A new function, Kvm::capIRQLineLayout2(), is added for checking the
status of KVM_CAP_ARM_IRQ_LINE_LAYOUT_2.

This fixes a compilation error on Arm systems.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/55964

Change-Id: Ia190e06ab451e0ff8d1c4833cd23b7de8852c6dd
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59310
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-05-03 17:09:05 +00:00
Hoa Nguyen
2938119f97 arch-arm: Fix GenericTimer param name in BaseArmKvmCPU
Per change [1], the new name for `int_virt` is `int_el1_virt`.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/58109

Change-Id: Idde4ac831c7a323b80272642e6a48b1c5e488135
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59309
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-05-03 17:09:05 +00:00
Giacomo Travaglini
9c9b3a5e3d arch-arm: Split purifyTaggedAddr in two sub-functions
This patch is splitting the purifyTaggedAddr helper in two
by introducing the maskTaggedAddress utility

* The first part computes the top bit of the address (computeAddrTop)
(This is required as the MSBs of a VA could be used to store
tags like in FEAT_Pauth)

* The second part applies some masking to the supplied
address (maskTaggedAddress) depending on the top bit to
purify the VA from the TAG

The motivation of this split will be clear in the next patch:
we want to memoize the expensive computeAddrTop. Memoizing
purifyTaggedAddr is inefficient as the first argument
is the VA of the memory request so multiple memory requests
will allocate multiple entries in the results cache and
memoization will rarely be used.

We will memoize the VA agnostic computeAddrTop instead

Change-Id: Ib3d8bb521be67a1f21c0891e753396299adf500b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59150
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-05-03 10:40:19 +00:00
Giacomo Travaglini
287bea8a4d arch-arm: PAuth inst disassembled with a capitalized first letter
This is not aligned with what we do for other Arm instructions.
This patch removes capitalization of the first letter:

Example

Xpaclri -> xpaclri

Change-Id: I04b3d3b386e34e1dceec940af7c43fc42f538722
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59229
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-04-29 09:15:46 +00:00
Giacomo Travaglini
f8589a4719 sim, arch-riscv: Remove Fault debug flag
There is already a Faults debug flag used by Arm and X86 so
having both Fault and Faults is highly confusing

Change-Id: Id5c17f19b51c6257dfc470d07ba050a9de7a9db3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59152
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-04-28 08:52:49 +00:00
Yu-hsin Wang
9e4c5537a4 fastmodel: Add CortexR52 model reset port
The model reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I15101bfe11dee40b63cc29c2befb610beb3d32aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58813
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-26 06:31:51 +00:00
Yu-hsin Wang
b4d924fdca fastmodel: Add CortexA76 model reset port
The model reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I9aacc398b299e26e4675f7229db1afc8f6c8a34f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58814
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-26 06:31:51 +00:00
zhongchengyong
29a39d9472 arch-riscv: RISCV call/ret instructions aren't decoded correctly
This change adds IsReturn and IsCall flag for RISC-V jump instructions
by define new "JumpConstructor" in standard.isa, and fixes target
overwriting in buildRetPC.

See RAS presentation in spec:
Section 2.5 Page 22 of https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
Or:
https://github.com/riscv/riscv-isa-manual/blob/master/src/rv32.tex#:~:text=Return%2Daddress%20prediction,%5Cend%7Btable%7D

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1139

Change-Id: I9728757c9f3f81bd498a0ba04664a003dbded3bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58209
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-21 06:34:40 +00:00
Jerin Joy
70fd98e807 arch-riscv: Added the Zbs bitmanip instructions
Added the bclr, bclri, bext, bexti, binv, binvi, bset, bseti
instructions.

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I126d659d973b250b642bd56b3b149f0ee6a3323e
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58632
Reviewed-by: Luming Wang <wlm199558@126.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-04-13 20:09:59 +00:00
Jerin Joy
df886bc8c1 arch-riscv: Added the Zbc bitmanip instructions
Added clmul, clmulh, clmulr instructions.

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I98dc76ddde052f56e32eabed12af87039def665b
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58631
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Luming Wang <wlm199558@126.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 20:09:59 +00:00
Jerin Joy
aee1622a6c arch-riscv: Added the Zba and Zbb bitmanip instructions
Zba instructions added:
add.uw, sh1add, sh1add.uw, sh2add, sh2add.uw, sh3add, sh3add.uw, slli.uw

Zbb instructions added:
andn, orn, xnor, clz, clzw, ctz, ctzw, cpop, cpopw, max, maxu, min,
minu, sext.b, sext.h, zext.h, rol, rolw, ror, rori, roriw, rorw, orc.b, rev8

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I056719f62eee89e0f085d1bf1fa182f9dfe614d8
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58630
Reviewed-by: Luming Wang <wlm199558@126.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 20:09:59 +00:00
Yu-hsin Wang
72255064d6 fastmodel: Export more CortexR52 reset pin
Change-Id: I20f34ae2061e886b35fe9439dbb8e25ce3571e4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58811
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 08:44:03 +00:00
Yu-hsin Wang
9dce95844a fastmodel: Export more CortexA76 reset pin
Change-Id: I386cf659fa77b2005f808fde51ef772ac0a57735
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58812
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 08:44:03 +00:00
Gabe Black
7392cd470e scons: Ensure the fast model license count is always at least 1.
Even though the default value for the license count is 1, it seems that
if fast model is disabled, kconfig will set it to 0. When creating a
cycle using itertools over a list with zero elements, it will raise a
StopIteration.

Even though we don't actually try to build any fast model components
in that case, we do still set them up with a license slot. If the
cycle iterator is essentially broken, that will prevent that from
working and break the build.

This change forces the license count to be at least 1, even if fast
model is disabled and the license count may be set to 0 in the config.

Change-Id: Ia8df256a8f292deb6fb6fa3c5f9a7d58c2b7f782
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58490
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-13 02:16:13 +00:00
Gabe Black
7cc384c308 arch: Eliminate the now unused read_code and write_code args.
Also eliminate the buildReadCode and buildWriteCode methods.

Change-Id: I27b1b87ab51a44b5d7280e29e22f38d97d968a65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49743
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-12 23:50:52 +00:00
Gabe Black
cfe3ed47a6 arch-x86: Override make(Read|Write) instead of (read|write)_code.
Change-Id: Iab077f58e19aa6bfeed555caa31a4c8b3d261059
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49741
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2022-04-12 23:50:38 +00:00
Matthew Poremba
b64467025d arch-vega: Implement SOP2 S_MUL_HI instructions
Two new 32-bit signed and unsigned variants of S_MUL were added in
gfx900 which operate similar to S_MUL expect they shift the product by
32 bits after multiplication. Tested with Histogram HIP-Sample and
b+tree in rodinia 3.0 HIP port.

Change-Id: I1bed32b17ccda7aa47f3b59528eb3304912d3610
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58473
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-11 17:06:43 +00:00
Matthew Poremba
e3f65393fd dev-amdgpu,arch-vega: Implement TLB invalidation logic
Add logic to collect pointers to all GPU TLBs in full system. Implement
the invalid TLBs PM4 packet. The invalidate is done functionally since
there is really no benefit to simulate it with timing and there is no
support in the TLB to do so. This allow application with much larger
data sets which may reuse device memory pages to work in gem5 without
possibly crashing due to a stale translation being leftover in the TLB.

Change-Id: Ia30cce02154d482d8f75b2280409abb8f8375c24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58470
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-08 17:12:32 +00:00
Chia-You Chen
fb173e4d2c fastmodel: use global option 'num_jobs' instead of hardcoded number
Change-Id: I2d3f0855c8475cd44b1012fddf6b695621b2347f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58689
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-07 08:09:42 +00:00
Giacomo Travaglini
39ed6e0373 cpu, arch-arm: Rename initiateSpecialMemCmd to initateMemMgmtCmd
This is aligning with the name of the generated memory requests

Change-Id: Ifdfa01477abf7ff597dce3b5cff78f9a27fdcbcc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58511
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-05 09:24:16 +00:00
Gabe Black
3b6ea3dfa9 scons: Add a tag for arm fastmodel and use it.
This avoids some python logic in the SConscript files, and explicit
references to the configuration system.

Change-Id: If6ee61bb8c23606859e60323b8ca2c5254dbdecc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58356
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-01 02:28:56 +00:00
Gabe Black
a5509c580c scons: Only warn about not finding fast model libs if it's enabled.
These warnings could be confusing and aren't useful if it's not.

Change-Id: Ie660f639a3d8ee3406153ceb771b1ba5d0df9225
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58355
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-01 02:28:56 +00:00
Gabe Black
3ae3b1a62f scons: Rework the fastmodel extract_var helper.
This helper extracts config variables and sets them up for use in
fast model tools. Rework this function for two purposes. First, ensure
that the ['CONF'] subdict is used consistently. It was used in one spot
in that function, but not anywhere else. Avoid those mistakes by
accessing the configuration dict only once, and then reusing the value.

Second, only print the values of those variables if they aren't empty.
That avoids extra log output for values which aren't set up and aren't
being used, while still exposing those values if they are set up. This
will print them even if they aren't being actively used, but are set up
and could be with other changes in the config.

Change-Id: Ia3ea76e6cb6b3347fd082112a1eaa8d594e06ca2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58354
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-01 02:28:56 +00:00
Gabe Black
4c6790ada6 scons: Stop the fast model project file parser from writing files.
PLY tries to write these little files into the SCons installation
directory, which it shouldn't even if it was allowed to. This avoids
a bunch of annoying messages about not having enough permission.

Change-Id: Ifd4eda9dd9f8518b3fd075e8a46de1b6c12c2127
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58353
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jui-min Lee <fcrh@google.com>
2022-04-01 02:28:56 +00:00
Gabe Black
d9a51177fc scons: Tone down a fast model error into a warning.
If a fast model static library can't be found, we should treat that as
a warning instead of an error, and pass back the original library name
so that it can at least be added and potentially come from somewhere
else.

In practice, this is important because gem5 will be configured by SCons
indirectly in the future, using kconfig based tools that SCons runs on
the user's behalf. If SCons is misconfigured or not configured, this
error can trip, preventing those tools from starting. That creates a
catch 22, since you'd need SCons to fix the config, and SCons can't
run because of the config.

We can avoid that problem by making SCons more lenient, so that it can
still run even if it doesn't find static libraries where it might have
expected to.

Change-Id: Iadfd823b61fe96b937c2650250487d290492f265
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58352
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-01 02:28:56 +00:00
Gabe Black
f56d43eadf scons: Get rid of an unused fast model variable.
This held the location of the license file, assuming it actually was a
license file and not a license server URL. If this variable was unset
because the fast model configuration parameters hadn't been set, then
the "File" would resolve to the local directory, and SCons would get
upset that you'd called the same path a directory and a file.

We can avoid this problem by just getting rid of this variable, since
it isn't used anyway.

Change-Id: I2ccda90b85f2c83c73816967d145e6bf45733f89
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58351
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-04-01 02:28:56 +00:00
Gabe Black
886154b958 arch: Split up src/dest register ID creation.
This will allow us to selectively change the RegID of an operand to, for
instance, convert it to InvalidRegClass just as a source so it never
actually gets read.

Change-Id: I9f8117cbb2088f8150080f815cdb5cb84bd7218e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49747
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-28 23:52:35 +00:00
Gabe Black
e6c0ba97db scons: Put all config variables in an env['CONF'] sub-dict.
This makes what are configuration and what are internal SCons variables
explicit and separate, and makes it unnecessary to call out what
variables to export to C++.

These variables will also be plumbed into and out of kconfiglib in later
changes.

Change-Id: Iaf5e098d7404af06285c421dbdf8ef4171b3f001
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56892
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-28 20:31:21 +00:00
Gabe Black
ee5c751fb5 arch-arm: Override makeRead and makeWrite in the ISA description.
Do that instead of using read_code or write_code.

Change-Id: I3f78f7a81c040336327e326b7196524ff6bedb10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49742
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-28 14:05:37 +00:00
Gabe Black
64d00f83c4 arch-x86: Ensure moving to %cs faults even in real mode.
It's always illegal to try to use the "mov" instruction to move a
selector into %cs. That was implemented for normal mov-s, but not for
the real mode version.

Change-Id: Ida8ec323fd7428ece583ad01cd5095d5f9630c9d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55825
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-27 00:55:44 +00:00
Gabe Black
141d44b979 arch-x86: Consider CPL in the decoder logic.
For instructions which simply require CPL0 (vs. requiring CPL is < IOPL,
or something else more complicated), this change either switches their
format so that they check that value before being returned, or adds a
comment marking them as privileged if they aren't yet implemented.

This change also makes the mov to/from CR and DR instructions more
particular, and returns an undefined instruction if the CR or DR index
is invalid.

Change-Id: I367d87a380a47428d458bda2ceecc1b983644704
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55891
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-27 00:55:44 +00:00
Gabe Black
00dd1b8ffc arch-x86: Add some formats for CPL0 only instructions.
These are essentially the same as the Inst and CondInst formats, except
it adds a CPL check. If the CPL check fails, a new instruction will be
returned which is only a vehicle for delivering a GP fault.

Change-Id: Ie1e7fb6a6c04082437c4d4a25adc3e03be09ac72
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55890
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-27 00:55:44 +00:00
Gabe Black
283ea24c8e arch-x86: Expose the current CPL to the decoder.
This value is already floating around, and there is essentially no
overhead for exposing it to the decoder. With that value, we can handle
instructions which generically need to run at CPL0.

Some instructions have other more complicated permissions checks, like
that the CPL needs to have some relation to the IOPL. Those checks will
have to be implemented by the instructions themselves, since the decoder
can't factor in all possible state values.

Change-Id: Ie93f4f13aae002f69330606c515f369c5706c655
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55889
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-27 00:55:44 +00:00
Gabe Black
cd4c295a22 arch-x86: Specialize LTR for 64 bit mode.
Like LDT descriptors, the TR descriptors are 128 bits in 64 bit mode,
and only 64 bits in other modes.

Change-Id: Iecfab8c5a90a8bfe0dff86880bc8f88c082ddc0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55886
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-27 00:55:44 +00:00
Gabe Black
013a90c969 arch-x86: Specialize LLDT for 64 bit and non-64 bit.
In 64 bit mode the LLDT has a 128 bit descriptor which takes up two
slots. In any other mode, the descriptor is still 64 bits.

Change-Id: I88d3758a66dec3482153df5ec08565427d6c9269
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55884
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-27 00:55:44 +00:00
Matthew Poremba
dd90417211 arch-vega: Bypass Ruby for functional page walks
Currently if a Ruby functional access fails to find an address in the
caches, it gives up. For functional page table walks we need to be able
to go all the way to memory. This adds a pointer to the system object
which allows the walker to get a pointer to device memory which can be
used to do a functional access directly to memory bypassing Ruby.

Change-Id: I0ead6e5e130a0d53021c44ae9221b167c6316ab2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57529
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-03-25 19:51:29 +00:00