Gabe Black caffb4e1ff arch: Detect and convert zero registers to InvalidRegClass. ...

Change-Id: Ic5e070d303bf05ed1640b441e498d879764b8778
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49745
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2022-06-07 18:26:22 +00:00

..

amdgpu

arch-vega: Implement SOP2 S_MUL_HI instructions

2022-04-11 17:06:43 +00:00

arm

arch: Detect and convert zero registers to InvalidRegClass.

2022-06-07 18:26:22 +00:00

generic

arch: Add an "as" template to dummy vec regs.

2022-03-16 15:02:44 +00:00

isa_parser

arch: Eliminate the now unused read_code and write_code args.

2022-04-12 23:50:52 +00:00

mips

arch: Detect and convert zero registers to InvalidRegClass.

2022-06-07 18:26:22 +00:00

null

arch: Remove TheISA::VecElem from arch/vecregs.hh.

2022-02-01 18:48:55 +00:00

power

scons: Put all config variables in an env['CONF'] sub-dict.

2022-03-28 20:31:21 +00:00

riscv

arch: Detect and convert zero registers to InvalidRegClass.

2022-06-07 18:26:22 +00:00

sparc

arch: Detect and convert zero registers to InvalidRegClass.

2022-06-07 18:26:22 +00:00

x86

arch: Detect and convert zero registers to InvalidRegClass.

2022-06-07 18:26:22 +00:00

micro_asm_test.py

arch:arch-x86: Fix style of some classes in the ucode assembler.

2022-03-19 13:37:33 +00:00

micro_asm.py

arch:arch-x86: Fix style of some classes in the ucode assembler.

2022-03-19 13:37:33 +00:00

SConscript

scons: Put all config variables in an env['CONF'] sub-dict.

2022-03-28 20:31:21 +00:00

SConsopts

scons: Make all sticky variables automatically exported.

2022-03-15 00:45:30 +00:00