Commit Graph

21063 Commits

Author SHA1 Message Date
Harshil Patel
b42d9fabf7 util: Added script to copy resources from mongodb (#510)
- This script copies all resources from a mongodb database locally The
script creates a resources.json and downloads all the resources. It also
updates the resources.json to point to these local downloads instead of
the cloud bucket.

Change-Id: I15480c4ba82bbf245425205c9c1ab7c0f3501cc3
2023-12-18 12:41:52 -08:00
Tiberiu Bucur
9b0bf33f79 sim: Remove trailing / from proc/meminfo special path (#689)
Note: A bug was identified in that the one of the special file paths,
namely /proc/meminfo contained an extra trailing /, implicitly making
the incorrect assumption that meminfo was a directory, when it is, in
fact, a (pseudo-)file. This was causing application in SE mode to fail
opening the meminfo pseudo-file with errno 13. This commit fixes this
issue.

Change-Id: I93fa81cab49645d70775088f1e634f067b300698
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
2023-12-17 22:07:39 -08:00
Giacomo Travaglini
a008cd2611 mem-ruby: Implement a dummy StashOnceShared/Unique (#688)
Stash requests will simply be discarded by the Home Node This will
return a CompI response to the RNF

Change-Id: I9c2ce5d4d42f380d1a554933d381cf8a8590ba22

Reviewed-by: Tiago Muck <tiago.muck@arm.com>

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-12-16 14:43:45 -08:00
Harshil Patel
c66862f6e3 arch-riscv: fix riscv matched board for se mode (#677) 2023-12-13 13:16:08 -08:00
Bobby R. Bruce
695c350f31 stdlib,resources: Fix obtaining gem5 Looppoint resources (#675)
There were two small bugs preventing gem5 from obtaining Looppoint
resources.

1. When obtained via a `WorkloadResource` there was an assert which
assumed the values in the resource's DB entry's `additional_parameter`
field were of type string. This is not the case. For Looppoint resources
there are additional parameters which are arrays.
2. Due to changes introduced in https://github.com/gem5/gem5/pull/625,
the Looppoint CSV and JSON files were not being downloaded when needed.
This was fixed by replacing access to the `local_path` variable with a
call to `get_local_path()`.
2023-12-13 12:49:57 -08:00
Bobby R. Bruce
da3e3b806d arch-riscv: squash walks with tlb hits in startWalkWrapper (#672)
Because each vector load is fragmented into 64 byte cache-aligned
chunks, and one page-table walk is issued per fragment on tlb miss,
walks start to accumulate on a pending queue, which is processed in a
blocking way (no pending walks can be issued while one is being
processed). This adds noticeable latency on vector loads when VLEN is
sufficiently large.

This commit fixes the issue by allowing walks to be squashed if a TLB
lookup hits just before starting the walk on `startWalkWrapper`. This
idea was taken from the ARM walker.
2023-12-13 12:45:40 -08:00
Saúl Adserias
78f23ad2df arch-riscv: squash walks with tlb hits in startWalkWrapper
Change-Id: I1bdfd7b2ee02ddee5a2d4c13bafc8c472f555f61
2023-12-13 16:40:46 +01:00
Giacomo Travaglini
8d09e95420 arch-arm: Partial SVE2 Implementation (#657)
Instructions added:

BGRP, RAX1, EOR3, BCAX,
XAR & TBX, PMUL, PMULLB/T, SMULLB/T and UMULLB/T

Move from gerrit [1]

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/70277

Change-Id: Ia135ba9300eae312b24342bcbda835fef6867113
2023-12-13 10:27:19 +00:00
Bobby R. Bruce
4eb81296b1 stdlib: Add get_local_path() call to Looppoint resources
Due to a change introduced in https://github.com/gem5/gem5/pull/625, a
gem5 resource will not download any external files until
`get_local_path()` is called. In the construction of the Looppoint
Resources this function was not called, the `local_path` variable was
called directly. As such, an error occured.

The downside of this fix is the Looppoint resources external files are
downloaded when `obtain_resource` is called, thus the bandwidth savings
introduced with https://github.com/gem5/gem5/pull/625 will not occur for
Looppoint resources. However, https://github.com/gem5/gem5/issues/644
proposes a fix which would supercede the
https://github.com/gem5/gem5/pull/625 solution.

Change-Id: I52181382a03e492ec1cb58b01e71bc4820af9ccc
2023-12-12 14:28:11 -08:00
Bobby R. Bruce
4adeb24a4f stdlib: Remove 'additional_params' value type assert
The value of a `WorkloadResource`'s additional parameter may not always
be a string. It can be any JSON value (integer, a list, a dict, ect.).
For Looppoint resources we have additional parameters such as a List of
region start points.

The assert inside workloads checking the type of the value breaks
certain usecase and is therefore removed in this commit.

Change-Id: Iecb1518082c28ab3872a8de888c76f0800261640
2023-12-12 14:23:04 -08:00
Bobby R. Bruce
eff08ba113 mem: Add a flag on AbstractMemory to control statistics collection (#656)
The stats initialization in the AbstractMemory allocates the space
according to the max requestors of the System. This may cause issues in
multiple system simulation.
Given there are two system A and B. A has one requestor and a memory,
while B has two requestors. When the requestor with requestor id 2
sending requests to the meomry in A, the simulator would crash because
requestor id 2 is out of the allocated space.

Current solution is adding a SysBridge between across A and B which
would rewrite the requestor id to a valid one. This solution works but
it needs to the bridge at the correct boundary which may not easy. In
addition, the stats would record a mapped data which may not accurate.

To reduce the complexity, we add an flag to AbstractMemory to control
the stats. If users don't want the statistics and want to solve the
cross system issue simply, users can disable the statistics collection.
We also makes the flag by default True to not disturb current users.
2023-12-12 13:13:30 -08:00
Bobby R. Bruce
c8cc193db8 arch,arch-riscv: Fix inst flag of RISC-V vector store macro instructions (#674)
Correct the instruction flags of RISC-V vector store instructions, such
as `vse64_v`, `vse32_v`. The `vse64_v` in `decoder.isa` is
`Mem_vc.as<uint64_t>()[i] = Vs3_ud[i];` and it will generate the code
`Mem.as<uint64_t>()[i] = Vs3[i];`. The current regex of assignRE only
mark the operand `Mem` as `dest` only if meet the formats like `Mem =
Rd` or `Mem[i] = Rd` because the code ` = Rd` or `[i] = Rd` match the
`assignRE` respectively. For the expression `Mem.as<uint64_t>()[i]`, the
operand `Mem` will falsely mark the operand as `src` because the code
`.as<uint64_t>()[i]` is not match the `assignRE`.

The PR will ensure the operand `Mem` is dest for the format like
`Mem.as<xxx>()[i] = yyy`.
2023-12-12 13:07:50 -08:00
Harshil Patel
bc12e7269d tests: fix gapbs and npb tests (#671)
Change-Id: I6090bde7903e302e501319b545fb4b06ef3e3df9
2023-12-12 12:33:22 -08:00
Yu-Cheng Chang
5a6901c405 configs: Make riscv/fs_linux work in build/ALL/gem5.opt (#655)
Change-Id: If9add7dc5e9c5600f769d27817da41466158942b
2023-12-12 08:23:28 -08:00
Bobby R. Bruce
37e4173351 arch-x86: Fix two_byte_opcodes.isa 0x6 -> 0x0 (#666)
This bug was introduced by https://github.com/gem5/gem5/pull/593 and
caused Issue https://github.com/gem5/gem5/issues/664.

Change-Id: Ia55de364ee8260e1fe315e37e1cffbc71ab229fb
2023-12-12 08:21:27 -08:00
Roger Chang
bedc3c597c arch: Fix inst flag of RISC-V vector store macro instructions
Correct the instruction flags of RISC-V vector store instructions, such
as `vse64_v`, `vse32_v`. The `vse64_v`  in `decoder.isa` is
`Mem_vc.as<uint64_t>()[i] = Vs3_ud[i];` and it will generate the code
`Mem.as<uint64_t>()[i] = Vs3[i];`. The current regex of assignRE only
mark the operand `Mem` as `dest` only if meet the formats like `Mem = Rd`
or `Mem[i] = Rd` because the code ` = Rd` or `[i] = Rd` match the
`assignRE` respectively. For the expression `Mem.as<uint64_t>()[i]`,
the operand `Mem` will falsely mark the operand as `src` because the
code `.as<uint64_t>()[i]` is not match the  `assignRE`.

The PR will ensure the operand `Mem` is dest for the format like
`Mem.as<xxx>()[i] = yyy`.

Change-Id: I9c57986a64f1efb81eb9c7ade90712b118e0788d
2023-12-12 17:04:31 +08:00
Roger Chang
10d344a942 arch-riscv: Fix the vector store indexed instructions declaration
Change-Id: I6f8701ef0819c22eda8cb20d09c40101f2d001a0
2023-12-12 16:36:49 +08:00
Bobby R. Bruce
ea1226119c arch-riscv: Update riscv matched board (#654)
- Update riscv matched board to work with new
RiscvBootloaderKernelWorkload

Change-Id: Ic20b964f33e73b76775bfe18798bd667f36253f6
2023-12-08 13:33:09 -08:00
Yu-Cheng Chang
10a0c950da stdlib: Fix the chi protocol of arm boot tests (#658)
Change-Id: I63f17a73b2e16bc26d9b41babc63439a6040791f
2023-12-07 16:10:45 -08:00
Giacomo Travaglini
81d3c6307d arch-arm: add Sve mla and mls indexed (#596)
This contains the implementation of mla and MLS index version
instructions from ARM SVE2 ISA specification.
2023-12-07 21:47:35 +00:00
Harshil Patel
0f0317ad16 Arch-riscv: Add chosen node
Change-Id: I458665caec08856cd8e61d2cd7a5b0dc5c35d469
2023-12-06 20:10:56 -08:00
Yu-hsin Wang
5de50cc9dd mem: update flag description and the if-block style
Change-Id: Iac727d38b88f1818aeeccf0d8de639fe18759074
2023-12-07 10:21:28 +08:00
Bobby R. Bruce
75544b2abf arch-riscv: Add PCEvent for RISCV FS Workload kernel panic/oops (#573)
Inspired by the similar feature in ARM's full system workload, this
change adds
an option to halt gem5 simulation if the guest system encounter kernel
panic
or kernel oops.

On RiscvISA::BootloaderKernelWorkload, by default, the simulation
will exit upon kernel panic, while kernel oops will not induce
simulation halt.
This is because the system will essentially do nop after a kernel panic,
while the
system might be still functional after a kernel oops.

Dumping kernel's dmesg is useful for diagonizing the cause of kernel
panic, so
ideally, we want to dump the guest's dmesg to the host. However, due to
a bug
described in [1], kernel v5.18+ dmesg might not be dumped properly.
Hence, the
dmesg will not be dumped to the host.

On RiscvISA::FsLinux, this feature is turned off by default as the
symbols from the
official RISC-V kernel resource are stripped from the binary. However,
if this feature
is enable, the dmesg will be dumped to the host system.

[1] https://github.com/gem5/gem5/issues/550

Change-Id: I8f52257727a3a789ebf99fdd4dffe5b3d89f1ebf
2023-12-06 10:58:23 -08:00
Yu-Cheng Chang
9bd61f217f configs: Fix issues after get_runtime_isa() #241 removed (#652)
1. Fix the wrong ISA detect of get_isa function
2. Fix the typo ObjectLIst.cpu_list
3. Fix missing PageTableWalkerCache
4. Fix the invalid default cpu_type paramter

Change-Id: I217ea8da8a6d8e712743a5b32c4c0669216ce6c4
2023-12-06 10:57:18 -08:00
Nitesh Narayana
d962d2588d arch-arm: This commit cleans .isa files
This commit cleans extra new lines from .isa files from this branch

Change-Id: I4087ed230aa041747038b49360c2aba3f82c0790
2023-12-06 16:03:21 +01:00
Matthias Boettcher
e4dccbea8a arch-arm: Partial SVE2 Implementation
Instructions added:

BGRP, RAX1, EOR3, BCAX,
XAR & TBX, PMUL, PMULLB/T, SMULLB/T and UMULLB/T

Change-Id: Ia135ba9300eae312b24342bcbda835fef6867113
2023-12-06 14:26:31 +00:00
Yu-hsin Wang
e2b3f0b8e4 mem: Add a flag on AbstractMemory to control statistics collection
The stats initialization in the AbstractMemory allocates the space
according to the max requestors of the System. This may cause issues in
multiple system simulation.
Given there are two system A and B. A has one requestor and a memory,
while B has two requestors. When the requestor with requestor id 2
sending requests to the meomry in A, the simulator would crash because
requestor id 2 is out of the allocated space.

Current solution is adding a SysBridge between across A and B which
would rewrite the requestor id to a valid one. This solution works but
it needs to the bridge at the correct boundary which may not easy. In
addition, the stats would record a mapped data which may not accurate.

To reduce the complexity, we add an flag to AbstractMemory to control
the stats. If users don't want the statistics and want to solve the
cross system issue simply, users can disable the statistics collection.
We also makes the flag by default True to not disturb current users.

Change-Id: Ibb46a63d216d4f310b3e920815a295073496ea6e
2023-12-06 13:41:37 +08:00
Harshil Patel
ee4c6a9bac arch-riscv: Update riscv matched boad
- Update riscv matched board to work with new
RiscvBootloaderKernelWorkload

Change-Id: Ic20b964f33e73b76775bfe18798bd667f36253f6
2023-12-05 14:54:12 -08:00
Nitesh Narayana
db8e1652e8 arch-arm: This commit uses existing template code for mla/s index
This includes mla/s index version  implementation using the existing template code
to avoid code repeatition.

Change-Id: If1de84e01dec638e206c979ca832308ebc904212
2023-12-05 23:40:06 +01:00
Matthew Poremba
f00d7f70a4 configs: Fix apu_se.py CPU type checks (#651)
The current checks do not work. Correct the CPU type names

Change-Id: I81778873df0567c4a8dabbbe659c4c7a39326f98
2023-12-04 19:14:46 -08:00
Hoa Nguyen
4a77d532b0 stdlib: Add Kernel Panic/Oops exit event to stdlib
RISCV full system workloads have the capability of exit the simulation loop
upon the guest's kernel panic/oops. This change adds more stdlib exit event types
to accommodate the corresponding gem5 exits upon the guest's kernel panic and
kernel oops.

Change-Id: I3a4f313711793a473c6f138ff831b948034d0bb6
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-12-04 16:52:14 -08:00
Hoa Nguyen
cf087d4d11 arch-riscv: Add PCEvent for RISCV FS Workload kernel panic/oops
Inspired by a similar feature in ARM's full system workload, this change adds
an option to halt gem5 simulation if the guest system encounter kernel panic
or kernel oops.

On RiscvISA::BootloaderKernelWorkload, by default, the simulation
will exit upon kernel panic, while kernel oops will not induce simulation halt.
This is because the system will essentially do nop after a kernel panic, while the
system might be still functional after a kernel oops.

Dumping kernel's dmesg is useful for diagonizing the cause of kernel panic, so
ideally, we want to dump the guest's dmesg to the host. However, due to a bug
described in [1], kernel v5.18+ dmesg might not be dumped properly. Hence, the
dmesg will not be dumped to the host.

On RiscvISA::FsLinux, this feature is turned off by default as the symbols from the
official RISC-V kernel resource are stripped from the binary. However, if this feature
is enable, the dmesg will be dumped to the host system.

[1] https://github.com/gem5/gem5/issues/550

Change-Id: I8f52257727a3a789ebf99fdd4dffe5b3d89f1ebf
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
Co-authored-by: Jason Lowe-Power <jason@lowepower.com>
2023-12-04 14:59:26 -08:00
Bobby R. Bruce
569e21f798 configs,stdlib,tests: Remove get_runtime_isa() (#241)
`get_runtime_isa()` has been deprecated for some time. It is a leftover
piece of code from when gem5 was compiled to a single ISA and that ISA
used to configure the simulated system to use that ISA. Since multi-ISA
compilations are possible, `get_runtime_isa()` should not be used.
Unless the gem5 binary is compiled to a single ISA, a failure will
occur.

The new proceedure for specify which ISA to use is by the setting of the
correct `BaseCPU` implementation. E.g., `X86SimpleTimingCPU` of
`ArmO3CPU`.

This patch removes the remaining `get_runtime_isa()` instances and
removes the function itself. The `SimpleCore` class has been updated to
allow for it's CPU factory to return a class, needed by scripts in
"configs/common".

The deprecated functionality in the standard library, which allowed for
the specifying of an ISA when setting up a processor and/or core has
also been removed. Setting an ISA is now manditory.

Fixes #216.
2023-12-04 09:53:35 -08:00
Nitish Arya
7b98641953 arch-riscv: correctly pass arguments to kernel with new bootloader+kernel (#635)
The [PR](https://github.com/gem5/gem5/pull/390) adds support for new
bootloader and linux kernel. However after applying the changes the
arguments are not passed correctly to the kernel resulting in kernel
panic during simulations. This commit fixes the issue.
2023-12-04 09:02:50 -08:00
Jason Lowe-Power
895944fa27 mem-ruby: Fix compile error in chi-dvm-funcs (#646)
clang correctly found that the functions `inCache`, `hasBeenPrefetched`
and `inMissQueue` had the wrong signatures in the DVM funcs files. These
functions are unused, so this change just updates their signatures.

Change-Id: Id669ff661e1c6c46eaf04ea1f17cd9866a9e49ed
2023-12-03 13:39:26 -08:00
Bobby R. Bruce
c718e94753 stdlib: Add comment to ShadowResource (#645)
This comment explains that this solution is a hack the solution created
by https://github.com/gem5/gem5/issues/644 should eventually replace it.
2023-12-03 13:38:59 -08:00
Harshil Patel
bad569a3f8 misc: update x86-npb-benchmarks.py to use suites (#587)
- updated the x86-npb-benchmarks.py to use npb workloads and suites.

The suites and workloads are not in the database are also waiting
feedback. I am attaching the JSON file here.

[npb_workloads_suite.json](https://github.com/gem5/gem5/files/13431116/npb_workloads_suite.json)

To run the x86-npb-benchmarks.py script use the
GEM5_RESOURCE_JSON_APPEND env variable. The full command is:
```
GEM5_RESOURCE_JSON_APPEND=[path to npb_workloads_suite.json] ./build/X86/gem5.opt configs/example/gem5_library/x86-npb-benchmarks.py --benchmark [benchmark]
```
Change-Id: I248e6452ea4122e9260e34e4368847660edae577
2023-12-03 13:23:46 -08:00
Harshil Patel
5eba3941f4 arch-riscv: fix o3 cpu stuck in spinlock bug (#641) 2023-12-03 13:22:46 -08:00
Hoa Nguyen
7a5052b3a0 arch-arm: Only build ArmCapstoneDisassembler when ISA is arm (#553)
Currently, if the Capstone header file is found in the host system,
scons will try to build the ArmCapstoneDisassembler regardless of the
gem5 target ISA. This is causing problem when the host has Capstone, but
the gem5 target ISA is not arm. Compiling gem5 in this case will cause
errors, e.g., ArmISA and ArmSystem is not found.

This change aims to prevent building the ArmCapstoneDisassembler when
the gem5 target ISA is not arm.

Ref:
[1] The Arm Capstone PR https://github.com/gem5/gem5/pull/494

Change-Id: I1e714d34aec8fe2a2af8cd351536951053a4d8a5
2023-12-03 13:22:11 -08:00
Harshil Patel
88c57e22de misc: update gapbs example to use suites (#607) 2023-12-03 13:21:37 -08:00
Bobby R. Bruce
21919addca Fix for gem5 Issue #550 (#636)
This Pull-Request addresses gem5 Issue #550. The code that dumps the
Dmesg buffer is now templated on the two variants of the `Metadata`
structure, and the correct one is chosen based on the detected Kernel
version.

To support this functionality, the pull request also adds Symbol Size
data to the loader Symbol Table, and adds a method to query the Kernel
Version from the image in guest memory. The new attributes in the Symbol
class are de-serialized speculatively, so no checkpoint upgrader is
required to support this change.
2023-12-01 18:06:20 -08:00
Richard Cooper
d9c870f641 sim: Rework the Linux Kernel exit events (#639)
This patch reworks the Linux Kernel panic and oops events. The code has
been re-factored to provide re-usable events that can be applied to all
ISAs from the base `KernelWorkload` `SimObject`. At the moment they are
installed for the Arm workloads.

This update also provides more configuration options that can be
specified using the new `KernelPanicOopsBehaviour` enum. The options are
applied to the Kernel Workload parameters `on_panic` and `on_oops` which
are available to all subclasses of `KernelWorkload`.

The main rationale for this reworking is to add the option to cleanly
exit the simulation after dumping the Dmesg buffer. Without this option,
the simulation would continue running after a Kernel panic. If system
components (e.g. a system timer) keep the event queue alive, this causes
the simulation to run slowly to the maximum allowed tick.
2023-12-01 17:33:59 -08:00
Jason Lowe-Power
ecb72b74f8 misc: Add gem5_build/ to .gitignore (#642)
The website's documentation on building gem5 now references
<gem5_base>/gem5_build in addition to <gem5_base>/build. So, we should
ignore files in that directory as well as the build directory.

Change-Id: Ie226545e04b885ce81b3c17e18b5052ed64af328
2023-12-01 17:05:41 -08:00
Bobby R. Bruce
500a4221a0 stdlib: Mv resource download to get_local_path and add ShadowResource (#625)
This change decouple's the downloading of a resource from it's data.
With this change the `obtain_resource` function returns the
`AbstractResource` implementation which contains the data. The resource
itself (e.g., the actual disk image, binary, file, etc.) is only
downloaded to the host system, if not already present, upon the
`get_local_path` call.

`get_local_path` is the function used by gem5 to ultimately load the
resource into a simulation, therefore this change ensures we only
download resources when they are loaded into a simulation.

This change is not ideal and comes with the following caveats:

1. The `downloader` function is created in `obtain_workload` and passed
to the `AbstractResource` implementation for later use. This function
comes with the following requirements:
    * The function will download the resource to `local_path`.
    * The function will not re-download the resources if already present
as this function is called _everytime_ `get_local_path` is called.
2. The directories needed to store `local_path` are created in
`obtain_workload` regardless. Ergo even if the resource is not used and
`get_local_path` is never called these directories are still created.


In keeping with this efficiency `ShadowResource` is introduced to allow
the storing of just the resource ID and Version of a resource with
additional information only obtained when requested.
2023-12-01 17:04:21 -08:00
Bobby R. Bruce
48f3cd1c0e stdlib: Integrate BootloaderKernelWorkload (#630)
This change does the following,

- Change the name of several python parameter names of the
RiscvBootloaderKernelWorkload. This is done to conform the expectation
from the stdlib, e.g., the kernel path must be `object_file`, and the
boot parameter must be `command_line`.
- Use RiscvBootloaderKernelWorkload by default for all full system
RISC-V simulations. RiscvBootloaderKernelWorkload is a superset of
RiscvFsWorkload.
2023-12-01 17:04:02 -08:00
Robert Hauser
84efeb976a systemc: Bugfix in TlmToGem5Bridge (#615)
In handleBeginReq, a timing request is sent. If the receiver rejects the
request, the bridge will save the pointers of the original transaction
object and the generated gem5 packet. After a recvReqRetry-signal and a
successful timing request, the variable for transaction object pointer,
but not for the gem5 packet, is set to nullptr. When a new transaction
with the phase BEGIN_REQ arrives, the assertion in handleBeginReq that
there is no pending gem5 packet fails.
Therefore, the variable pendingPacket has to be set to nullptr in
recvReqRetry after a successful timing request too.

Change-Id: I876f8f88e1893e8fdfa3441ed2ae5ddc39cef2ce

Co-authored-by: Robert Hauser <robert.hauser@uni-rostock.de>
2023-12-01 16:18:51 -08:00
Harshil Patel
9d108826b0 tests: fix artifact reference in HACC tests (#638)
Change-Id: I181f17a598885b59c186ff7e810d5b8b3b304e05
2023-12-01 15:19:17 -08:00
Matt Sinclair
bd2838d18e mem-ruby: update CacheMemory RubyCache debug prints (#637)
Update the RubyCache debug flag prints in CacheMemory to be more
descriptive and make clearer what is happening in a given function.
This makes it easier to determine what is happening when looking at the
RubyCache debug flags prints.

Change-Id: Ieee172b6df0d100f4b1e8fe4bba872fc9cf65854
2023-12-01 16:11:52 -06:00
Hoa Nguyen
39fd61d7dd misc: Fix precommit install (#634)
Previously, the `subprocess` module was used to execute shell command
installing precommit hook. However, after #431 [1], the import of the
`subprocess` module was overriden by `asyncio.subprocess`, which has a
different API to execute the shell command. This change removes the
`asyncio.subprocess` import.

[1] https://github.com/gem5/gem5/pull/431

Change-Id: I9a7d51f85518089d258ab57c5d849a36dcf128e9

Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-12-01 14:03:59 -08:00
Richard Cooper
ccb8b30967 misc: Update Dmesg dump for changes to printk in Linux v5.18+.
Linux v5.18+ changed the format of one of the data structures used to
implement the printk ring buffer. This caused the gem5 feature to dump
the printk messages on Kernel panic to fail for Kernels 5.18.0 and
later.

This patch updates the printk messages dump feature to support the new
printk ring buffer format when Kernels 5.18 and later are detected.

This patch addresses gem5 Issue #550:
https://github.com/gem5/gem5/issues/550

Change-Id: I533d539eafb83c44eeb4b9fbbcdd9c172fd398e6
Reported-by: Hoa Nguyen <hn@hnpl.org>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2023-12-01 22:00:36 +00:00