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arch-arm: This commit uses existing template code for mla/s index

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This includes mla/s index version  implementation using the existing template code
to avoid code repeatition.

Change-Id: If1de84e01dec638e206c979ca832308ebc904212
This commit is contained in:
Nitesh Narayana
2023-12-05 23:40:06 +01:00
parent 35ccd7f907
commit db8e1652e8
5 changed files with 29 additions and 126 deletions
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20
src/arch/arm/insts/sve.cc
View File

@@ -435,26 +435,6 @@ SveTerPredOp::generateDisassembly(
return ss.str();
}
std::string
SveTerIndexedOp::generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
printVecReg(ss, dest, true);
ccprintf(ss, ", ");
printVecReg(ss, op1, true);
ccprintf(ss, ", ");
printVecReg(ss, op2, true);
ccprintf(ss, "[");
ccprintf(ss, "%lu", imm);
ccprintf(ss, "]");
return ss.str();
}
std::string
SveTerUnpredOp::generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const

21
src/arch/arm/insts/sve.hh
View File

@@ -498,27 +498,6 @@ class SveTerPredOp : public ArmStaticInst
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Ternary, destructive, unpredicated , !INDEXED! SVE Instruction
class SveTerIndexedOp : public ArmStaticInst
{
protected:
RegIndex dest, op1, op2;
uint16_t imm;
uint8_t esize;
SveTerIndexedOp(const char* mnem, ExtMachInst _machInst,
OpClass __opClass, RegIndex _dest,
RegIndex _op1, RegIndex _op2, uint16_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2) , imm(_imm)
{}
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Ternary, destructive, unpredicated SVE instruction.
class SveTerUnpredOp : public ArmStaticInst
{

48
src/arch/arm/isa/formats/sve_2nd_level.isa
View File

@@ -250,50 +250,56 @@ namespace Aarch64
{
RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
RegIndex zm ;
//= (RegIndex) (uint8_t) bits(machInst, 19, 16);
uint8_t size = bits(machInst, 23, 22);
uint16_t imm;
uint8_t opc = (bits(machInst, 10));
switch(size) {
case 0b00:
case 0b01:
zm = (RegIndex)(uint8_t)bits(machInst, 18, 16);
imm = (uint16_t)(bits(machInst, 22) << 2)
{
RegIndex zm_16 = (RegIndex)(uint8_t)bits(machInst, 18, 16);
uint8_t imm_16 = (uint8_t)(bits(machInst, 22) << 2)
| bits(machInst, 20, 19);
switch(opc) {
case 0x0: return new Sve2Mlai<int16_t>(
machInst, zda, zn, zm, imm);
case 0x1: return new Sve2Mlsi<int16_t>(
machInst, zda, zn, zm, imm);
}
switch(opc)
{
case 0x0: return new Sve2Mlai<int16_t>(
machInst, zda, zn, zm_16, imm_16);
case 0x1: return new Sve2Mlsi<int16_t>(
machInst, zda, zn, zm_16, imm_16);
}
}
break;
case 0b10:
zm = (RegIndex)(uint8_t)bits(machInst, 18, 16);
imm = (uint16_t)bits(machInst, 20, 19);
{
RegIndex zm_32 = (RegIndex)(uint8_t)bits(machInst, 18, 16);
uint8_t imm_32 = (uint8_t)bits(machInst, 20, 19);
switch(opc) {
case 0x0: return new Sve2Mlai<int32_t>(
machInst, zda, zn, zm, imm);
machInst, zda, zn, zm_32, imm_32);
case 0x1: return new Sve2Mlsi<int32_t>(
machInst, zda, zn, zm, imm);
machInst, zda, zn, zm_32, imm_32);
}
}
break;
case 0b11:
zm = (RegIndex)(uint8_t)bits(machInst, 19, 16);
imm = (uint16_t)bits(machInst, 20);
{
RegIndex zm_64 = (RegIndex)(uint8_t)bits(machInst, 19, 16);
uint8_t imm_64 = (uint8_t)bits(machInst, 20);
switch(opc) {
case 0x0: return new Sve2Mlai<int64_t>(
machInst, zda, zn, zm, imm);
machInst, zda, zn, zm_64, imm_64);
case 0x1: return new Sve2Mlsi<int64_t>(
machInst, zda, zn, zm, imm);
machInst, zda, zn, zm_64, imm_64);
}
}
break;
}
return new Unknown64(machInst);
} // decodeSveMultiplyAccIndexed

32
src/arch/arm/isa/insts/sve.isa
View File

@@ -2096,34 +2096,6 @@ let {{
'class_name' : 'Sve' + Name}
exec_output += SveOpExecDeclare.subst(substDict)
# Generates definitions for ternary SVE instructions (indexed)
def sveTerInstIndexed(name, Name, opClass, types, op, decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
for (unsigned i = 0; i < eCount; i++) {
int segbase = i - i % (128 / sizeof(Element));
int s = segbase + imm;
const Element& srcElem1 = AA64FpOp1_x[i];
const Element& srcElem2 = AA64FpOp2_x[s];
Element destElem = AA64FpDestMerge_x[i];
'''
code += f"{op} \n"
code += ''' AA64FpDest_x[i] = destElem;
}'''
iop = ArmInstObjParams(name, 'Sve2' + Name+ 'i', 'SveTerIndexedOp',
{'code': code, 'op_class': opClass}, [])
header_output += SveTerIndexedOpDeclare.subst(iop)
exec_output += SveOpExecute.subst(iop)
for type in types:
substDict = {'targs' : type,
'class_name' : 'Sve2' + Name + "i"}
exec_output += SveOpExecDeclare.subst(substDict)
# Generates definitions for ternary SVE intructions (always predicated -
# merging)
def sveTerInst(name, Name, opClass, types, op, decoder='Generic'):
@@ -4276,13 +4248,13 @@ let {{
mlaCode = 'destElem += srcElem1 * srcElem2;'
sveTerInst('mla', 'Mla', 'SimdMultAccOp', signedTypes, mlaCode)
#indexed
sveTerInstIndexed('mla', 'Mla', 'SimdMultAccOp', signedTypes, mlaCode)
sveTerIdxInst('mla', '2Mlai', 'SimdMultAccOp', signedTypes, mlaCode)
# MLS
mlsCode = 'destElem -= srcElem1 * srcElem2;'
sveTerInst('mls', 'Mls', 'SimdMultAccOp', signedTypes, mlsCode)
#indexed
sveTerInstIndexed('mls', 'Mls', 'SimdMultAccOp', signedTypes, mlsCode)
sveTerIdxInst('mls', '2Mlsi', 'SimdMultAccOp', signedTypes, mlsCode)
# ADCLT
adcltCode = 'res = srcElem1 + srcElem2 + carryIn;'

34
src/arch/arm/isa/templates/sve.isa
View File

@@ -517,40 +517,6 @@ class %(class_name)s : public %(base_class)s
def template SveTerIndexedOpDeclare {{
/*
For mla indexed version as it is not included in gem5 right now.
Using ternary ops but all ops are vector regs.
index is the imm here. (name can be changed)
*/
template <class _Element>
class %(class_name)s : public %(base_class)s
{
//static_assert(sizeof(_SElementA) == sizeof(_SElementB),
// "Source elements must have the same size.");
private:
%(reg_idx_arr_decl)s;
protected:
typedef _Element Element;
typedef _Element TPElem;
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2, uint16_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2,_imm)
{
%(set_reg_idx_arr)s;
%(constructor)s;
esize = sizeof(Element);
}
Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template SveMatMulOpDeclare {{