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arch-riscv: fix riscv matched board for se mode (#677)

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Harshil Patel
2023-12-13 13:16:08 -08:00
committed by GitHub
parent 695c350f31
commit c66862f6e3
1 changed files with 12 additions and 8 deletions
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20
src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
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@@ -312,14 +312,18 @@ class RISCVMatchedBoard(
@overrides(AbstractSystemBoard)
def _pre_instantiate(self):
if len(self._bootloader) > 0:
self.workload.bootloader_addr = 0x0
self.workload.bootloader_filename = self._bootloader[0]
self.workload.kernel_addr = 0x80200000
self.workload.entry_point = 0x80000000 # Bootloader starting point
else:
self.workload.kernel_addr = 0x0
self.workload.entry_point = 0x80000000
if self._fs:
if len(self._bootloader) > 0:
self.workload.bootloader_addr = 0x0
self.workload.bootloader_filename = self._bootloader[0]
self.workload.kernel_addr = 0x80200000
self.workload.entry_point = (
0x80000000 # Bootloader starting point
)
else:
self.workload.kernel_addr = 0x0
self.workload.entry_point = 0x80000000
self._connect_things()
def generate_device_tree(self, outdir: str) -> None: