From c66862f6e3fbad5b0066c847aea8c5aef62b367e Mon Sep 17 00:00:00 2001
From: Harshil Patel <hpppatel@ucdavis.edu>
Date: Wed, 13 Dec 2023 13:16:08 -0800
Subject: [PATCH] arch-riscv: fix riscv matched board for se mode (#677)

---
 .../riscvmatched/riscvmatched_board.py        | 20 +++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
index f4e4b381a1..0de69a40f2 100644
--- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
+++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py
@@ -312,14 +312,18 @@ class RISCVMatchedBoard(
 
     @overrides(AbstractSystemBoard)
     def _pre_instantiate(self):
-        if len(self._bootloader) > 0:
-            self.workload.bootloader_addr = 0x0
-            self.workload.bootloader_filename = self._bootloader[0]
-            self.workload.kernel_addr = 0x80200000
-            self.workload.entry_point = 0x80000000  # Bootloader starting point
-        else:
-            self.workload.kernel_addr = 0x0
-            self.workload.entry_point = 0x80000000
+        if self._fs:
+            if len(self._bootloader) > 0:
+                self.workload.bootloader_addr = 0x0
+                self.workload.bootloader_filename = self._bootloader[0]
+                self.workload.kernel_addr = 0x80200000
+                self.workload.entry_point = (
+                    0x80000000  # Bootloader starting point
+                )
+            else:
+                self.workload.kernel_addr = 0x0
+                self.workload.entry_point = 0x80000000
+
         self._connect_things()
 
     def generate_device_tree(self, outdir: str) -> None: