configs: Fix issues after get_runtime_isa() #241 removed (#652)

1. Fix the wrong ISA detect of get_isa function
2. Fix the typo ObjectLIst.cpu_list
3. Fix missing PageTableWalkerCache
4. Fix the invalid default cpu_type paramter

Change-Id: I217ea8da8a6d8e712743a5b32c4c0669216ce6c4

configs/common/CacheConfig.py

@@ -148,9 +148,9 @@ def config_cache(options, system):
             dcache = dcache_class(**_get_cache_opts("l1d", options))
 
             # If we are using ISA.X86 or ISA.RISCV, we set walker caches.
-            if ObjectList.CPUList().get_isa(options.cpu_type) in [
-                ISA.RiscvCPU,
-                ISA.X86CPU,
+            if ObjectList.cpu_list.get_isa(options.cpu_type) in [
+                ISA.RISCV,
+                ISA.X86,
             ]:
                 iwalkcache = PageTableWalkerCache()
                 dwalkcache = PageTableWalkerCache()
@@ -191,7 +191,7 @@ def config_cache(options, system):
             # on these names.  For simplicity, we would advise configuring
             # it to use this naming scheme; if this isn't possible, change
             # the names below.
-            if ObjectList.CPUList().get_isa(options.cpu_type) in [
+            if ObjectList.cpu_list.get_isa(options.cpu_type) in [
                 ISA.X86,
                 ISA.ARM,
                 ISA.RISCV,

configs/common/Caches.py

@@ -86,3 +86,14 @@ class IOCache(Cache):
     mshrs = 20
     size = "1kB"
     tgts_per_mshr = 12
+
+
+class PageTableWalkerCache(Cache):
+    assoc = 2
+    tag_latency = 2
+    data_latency = 2
+    response_latency = 2
+    mshrs = 10
+    size = "1kB"
+    tgts_per_mshr = 12
+    is_read_only = False

configs/common/CpuConfig.py

@@ -36,6 +36,17 @@
 import m5.objects
 from m5 import fatal
 
+from gem5.isas import ISA
+
+isa_string_map = {
+    ISA.X86: "X86",
+    ISA.ARM: "Arm",
+    ISA.RISCV: "Riscv",
+    ISA.SPARC: "Sparc",
+    ISA.POWER: "Power",
+    ISA.MIPS: "Mips",
+}
+
 
 def config_etrace(cpu_cls, cpu_list, options):
     if issubclass(cpu_cls, m5.objects.DerivO3CPU):

configs/common/ObjectList.py

@@ -166,26 +166,15 @@ class CPUList(ObjectList):
 
         cls = self.get(name)
 
-        def class_exist(className: str) -> bool:
-            """Check if a class exists."""
-            import types
-
-            result = False
-            try:
-                result = eval("type(" + className + ")") == types.ClassType
-            except NameError:
-                pass
-            return result
-
-        if class_exist(m5.objects.X86CPU) and issubclass(
+        if hasattr(m5.objects, "X86CPU") and issubclass(
             cls, m5.objects.X86CPU
         ):
             return ISA.X86
-        elif class_exist(m5.objects.ArmCPU) and issubclass(
+        elif hasattr(m5.objects, "ArmCPU") and issubclass(
             cls, m5.objects.ArmCPU
         ):
             return ISA.ARM
-        elif class_exist(m5.objects.RiscvCPU) and issubclass(
+        elif hasattr(m5.objects, "RiscvCPU") and issubclass(
             cls, m5.objects.RiscvCPU
         ):
             return ISA.RISCV

configs/common/Options.py

@@ -38,7 +38,10 @@
 
 import argparse
 
-from common import ObjectList
+from common import (
+    CpuConfig,
+    ObjectList,
+)
 from common.Benchmarks import *
 
 import m5
@@ -242,6 +245,7 @@ def addNoISAOptions(parser):
 def addCommonOptions(parser):
     # start by adding the base options that do not assume an ISA
     addNoISAOptions(parser)
+    isa = list(get_supported_isas())[0]
 
     # system options
     parser.add_argument(
@@ -252,7 +256,7 @@ def addCommonOptions(parser):
     )
     parser.add_argument(
         "--cpu-type",
-        default=list(get_supported_isas())[0].name + "AtomicSimpleCPU",
+        default=CpuConfig.isa_string_map[isa] + "AtomicSimpleCPU",
         choices=ObjectList.cpu_list.get_names(),
         help="type of cpu to run with",
     )
@@ -583,7 +587,7 @@ def addCommonOptions(parser):
     parser.add_argument(
         "--restore-with-cpu",
         action="store",
-        default="AtomicSimpleCPU",
+        default=CpuConfig.isa_string_map[isa] + "AtomicSimpleCPU",
         choices=ObjectList.cpu_list.get_names(),
         help="cpu type for restoring from a checkpoint",
     )

configs/common/Simulation.py

@@ -81,9 +81,9 @@ def setCPUClass(options):
             TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu)
     elif options.fast_forward:
         CPUClass = TmpClass
+        CPUISA = ObjectList.cpu_list.get_isa(options.cpu_type)
         TmpClass = getCPUClass(
-            ObjectList.CPUList().get_isa(options.cpu_type).name
-            + "AtomicSimpleCPU"
+            CpuConfig.isa_string_map[CPUISA] + "AtomicSimpleCPU"
         )
         test_mem_mode = "atomic"
 

configs/deprecated/example/fs.py

@@ -382,7 +382,7 @@ else:
 
 np = args.num_cpus
 
-isa = ObjectList.CPUList.get_isa(args.cpu_type)
+isa = ObjectList.cpu_list.get_isa(args.cpu_type)
 test_sys = build_test_system(np, isa)
 
 if len(bm) == 2:

configs/deprecated/example/se.py

@@ -149,7 +149,7 @@ if args.bench:
 
     for app in apps:
         try:
-            if ObjectList.CPUList().get_isa(args.cpu_type) == ISA.ARM:
+            if ObjectList.cpu_list.get_isa(args.cpu_type) == ISA.ARM:
                 exec(
                     "workload = %s('arm_%s', 'linux', '%s')"
                     % (app, args.arm_iset, args.spec_input)

configs/example/hmc_hello.py

@@ -51,7 +51,7 @@ parser.add_argument(
     "--cpu-type",
     type=str,
     default="X86TimingSimpleCPU",
-    choices=ObjectList.CPUList().get_names(),
+    choices=ObjectList.cpu_list.get_names(),
     help="CPU model to use",
 )
 HMC.add_options(parser)
@@ -65,7 +65,7 @@ clk = "1GHz"
 vd = VoltageDomain(voltage="1V")
 system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
 # create a CPU
-system.cpu = ObjectList().get(options.cpu_type)()
+system.cpu = ObjectList.cpu_list.get(options.cpu_type)()
 # config memory system
 MemConfig.config_mem(options, system)
 # hook the CPU ports up to the membus
@@ -81,7 +81,7 @@ system.system_port = system.membus.cpu_side_ports
 
 binary = (
     "tests/test-progs/hello/bin/"
-    + ObjectList.CPUList().get_isa(options.cpu_type).name.lower()
+    + ObjectList.cpu_list.get_isa(options.cpu_type).name.lower()
     + "/linux/hello"
 )
 

configs/ruby/Ruby.py

@@ -331,8 +331,8 @@ def send_evicts(options):
     # 2. The x86 mwait instruction is built on top of coherence invalidations
     # 3. The local exclusive monitor in ARM systems
 
-    if isinstance(
-        options.cpu_type, DerivO3CPU
-    ) or ObjectList.CPUList().get_isa(options.cpu_type) in [ISA.X86, ISA.ARM]:
+    if isinstance(options.cpu_type, DerivO3CPU) or ObjectList.cpu_list.get_isa(
+        options.cpu_type
+    ) in [ISA.X86, ISA.ARM]:
         return True
     return False