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arch-arm: add Sve mla and mls indexed (#596)

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This contains the implementation of mla and MLS index version
instructions from ARM SVE2 ISA specification.
This commit is contained in:
Giacomo Travaglini
2023-12-07 21:47:35 +00:00
committed by GitHub
parent 75544b2abf d962d2588d
commit 81d3c6307d
2 changed files with 70 additions and 0 deletions
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64
src/arch/arm/isa/formats/sve_2nd_level.isa
View File

@@ -245,6 +245,65 @@ namespace Aarch64
return new Unknown64(machInst);
} // decodeSveIntMulAdd
StaticInstPtr
decodeSveMultiplyAccIndexed(ExtMachInst machInst)
{
RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t size = bits(machInst, 23, 22);
uint8_t opc = (bits(machInst, 10));
switch(size) {
case 0b00:
case 0b01:
{
RegIndex zm_16 = (RegIndex)(uint8_t)bits(machInst, 18, 16);
uint8_t imm_16 = (uint8_t)(bits(machInst, 22) << 2)
| bits(machInst, 20, 19);
switch(opc)
{
case 0x0: return new Sve2Mlai<int16_t>(
machInst, zda, zn, zm_16, imm_16);
case 0x1: return new Sve2Mlsi<int16_t>(
machInst, zda, zn, zm_16, imm_16);
}
}
break;
case 0b10:
{
RegIndex zm_32 = (RegIndex)(uint8_t)bits(machInst, 18, 16);
uint8_t imm_32 = (uint8_t)bits(machInst, 20, 19);
switch(opc) {
case 0x0: return new Sve2Mlai<int32_t>(
machInst, zda, zn, zm_32, imm_32);
case 0x1: return new Sve2Mlsi<int32_t>(
machInst, zda, zn, zm_32, imm_32);
}
}
break;
case 0b11:
{
RegIndex zm_64 = (RegIndex)(uint8_t)bits(machInst, 19, 16);
uint8_t imm_64 = (uint8_t)bits(machInst, 20);
switch(opc) {
case 0x0: return new Sve2Mlai<int64_t>(
machInst, zda, zn, zm_64, imm_64);
case 0x1: return new Sve2Mlsi<int64_t>(
machInst, zda, zn, zm_64, imm_64);
}
}
break;
}
return new Unknown64(machInst);
} // decodeSveMultiplyAccIndexed
StaticInstPtr
decodeSveIntMatMulAdd(ExtMachInst machInst)
{
@@ -3920,6 +3979,11 @@ namespace Aarch64
return decodeSveIntegerDotProductIndexed(machInst);
case 0b11:
return decodeSveMixedSignDotProductIndexed(machInst);
// for mla/s indexed , can be renamed
case 0b01:
return decodeSveMultiplyAccIndexed(machInst);
default:
return new Unknown64(machInst);
}

6
src/arch/arm/isa/insts/sve.isa
View File

@@ -4244,9 +4244,15 @@ let {{
# MLA
mlaCode = 'destElem += srcElem1 * srcElem2;'
sveTerInst('mla', 'Mla', 'SimdMultAccOp', signedTypes, mlaCode)
#indexed
sveTerIdxInst('mla', '2Mlai', 'SimdMultAccOp', signedTypes, mlaCode)
# MLS
mlsCode = 'destElem -= srcElem1 * srcElem2;'
sveTerInst('mls', 'Mls', 'SimdMultAccOp', signedTypes, mlsCode)
#indexed
sveTerIdxInst('mls', '2Mlsi', 'SimdMultAccOp', signedTypes, mlsCode)
# ADCLT
adcltCode = 'res = srcElem1 + srcElem2 + carryIn;'
sveTerInstUnpred('adclt', 'Adclt', 'VectorIntegerArithOp', unsignedTypes,