diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats/sve_2nd_level.isa
index 86c174d7c4..dce4f9e998 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -245,6 +245,65 @@ namespace Aarch64
         return new Unknown64(machInst);
     }  // decodeSveIntMulAdd
 
+    StaticInstPtr
+    decodeSveMultiplyAccIndexed(ExtMachInst machInst)
+    {
+        RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+        RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+        uint8_t size = bits(machInst, 23, 22);
+        uint8_t opc = (bits(machInst, 10));
+
+       switch(size) {
+            case 0b00:
+            case 0b01:
+            {
+
+                RegIndex zm_16 = (RegIndex)(uint8_t)bits(machInst, 18, 16);
+                uint8_t imm_16 = (uint8_t)(bits(machInst, 22) << 2)
+                | bits(machInst, 20, 19);
+                switch(opc)
+                    {
+                        case 0x0: return new Sve2Mlai<int16_t>(
+                            machInst, zda, zn, zm_16, imm_16);
+                        case 0x1: return new Sve2Mlsi<int16_t>(
+                            machInst, zda, zn, zm_16, imm_16);
+                    }
+            }
+                break;
+
+            case 0b10:
+            {
+
+                RegIndex zm_32 = (RegIndex)(uint8_t)bits(machInst, 18, 16);
+                uint8_t imm_32 = (uint8_t)bits(machInst, 20, 19);
+                switch(opc) {
+                    case 0x0: return new Sve2Mlai<int32_t>(
+                        machInst, zda, zn, zm_32, imm_32);
+                    case 0x1: return new Sve2Mlsi<int32_t>(
+                        machInst, zda, zn, zm_32, imm_32);
+                }
+            }
+                break;
+
+            case 0b11:
+            {
+
+                RegIndex zm_64 = (RegIndex)(uint8_t)bits(machInst, 19, 16);
+                uint8_t imm_64 = (uint8_t)bits(machInst, 20);
+                switch(opc) {
+                    case 0x0: return new Sve2Mlai<int64_t>(
+                        machInst, zda, zn, zm_64, imm_64);
+                    case 0x1: return new Sve2Mlsi<int64_t>(
+                        machInst, zda, zn, zm_64, imm_64);
+                }
+            }
+            break;
+        }
+
+        return new Unknown64(machInst);
+
+    } // decodeSveMultiplyAccIndexed
+
     StaticInstPtr
     decodeSveIntMatMulAdd(ExtMachInst machInst)
     {
@@ -3920,6 +3979,11 @@ namespace Aarch64
                 return decodeSveIntegerDotProductIndexed(machInst);
               case 0b11:
                 return decodeSveMixedSignDotProductIndexed(machInst);
+
+                // for mla/s indexed , can be renamed
+              case 0b01:
+                return decodeSveMultiplyAccIndexed(machInst);
+
               default:
                 return new Unknown64(machInst);
             }
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 9999843b59..e0e44cdf3d 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -4244,9 +4244,15 @@ let {{
     # MLA
     mlaCode = 'destElem += srcElem1 * srcElem2;'
     sveTerInst('mla', 'Mla', 'SimdMultAccOp', signedTypes, mlaCode)
+    #indexed
+    sveTerIdxInst('mla', '2Mlai', 'SimdMultAccOp', signedTypes, mlaCode)
+
     # MLS
     mlsCode = 'destElem -= srcElem1 * srcElem2;'
     sveTerInst('mls', 'Mls', 'SimdMultAccOp', signedTypes, mlsCode)
+    #indexed
+    sveTerIdxInst('mls', '2Mlsi', 'SimdMultAccOp', signedTypes, mlsCode)
+
     # ADCLT
     adcltCode = 'res = srcElem1 + srcElem2 + carryIn;'
     sveTerInstUnpred('adclt', 'Adclt', 'VectorIntegerArithOp', unsignedTypes,