Added save and restore checkpoint tests for arm-hello, x86-hello, x86-fs, power-hello
Added mips and sparc test but mips does not support checkpoint and there is a bug in sparc.
Added test file to run the tests.
Change-Id: I2d3b96f95ee08aae921de9a885ac5be77d49f326
Due to a 60GB limit on the VMs the gem5 project's GitHub Actions
self-hosted Runners execute within, we cannot run tests which need to
download the gem5 Resource's PARSEC disk image (v1.0.0,
http://resources.gem5.org/resources/x86-parsec?version=1.0.0). This
image, 33GB, is too big and causes our runners to run out of disk space
and fail.
These changes can be reverted when we are able to increase the size of
our VMs.
The x86-parsec gem5 Resource (v1.0.0,
http://resources.gem5.org/resources/x86-parsec?version=1.0.0) is 33GB.
The gem5 GitHub Actions self-hosted runners do not have enough Disk
Space in the VMs they are run to download this. Ergo we skip it.
Change-Id: I290fe265f03ceca65b2bed87e9f4a4ad601e0fc1
This argument allows the passing of IDs of resources which should be
skipped for this check.
Note: A current limitation here is you cannot specify the version of a
resource. Passing the ID of a resource to this will skip the downloading
for all versions of that resource.
Change-Id: Ifdb7c2b71553126fd52a3d286897ed5dd8e98f7c
These tests are disabled due our GitHub Actions self-hosted Runners
having a 60GB of disk space. The PARSEC Disk Image Resource (v1.0.0,
http://resources.gem5.org/resources/x86-parsec?version=1.0.0) is 33GB
and is simply too big to download and unzip for these tests.
These tests can be reenabled when this issue is resolved.
Change-Id: I9a63aa1903cea3ce7942bdc85bcd0b24761d2f29
There was another missing file in the configs for the fs tests,
so this should allow the switcheroo tests to pass.
Change-Id: Ic4e26cceeb9209f176158b80eaaba88b47968c39
The dailies timed out as they were running the entire directory of tests
due to a wrong variable name being used. In addition, the names of tests
were adjusted to include the matrix type so the artifacts won't
overwrite each other
The configs directory for the fs tests was missing the
checkpoint.py file, causing some of the CI tests to fail.
Change-Id: Ifbd775ad658f96d06bea7bee554fe3bedcf5a5b5
* Solves issue #106 by updating the cpts with the necessary vector
registers.
Change-Id: Ifeda90e96097f0b0a65338c6b22a8258c932c585
util: clear vector_element field
Change-Id: I6c9ec4e71f66722b26de030fa139cd626bdb24dc
"tests/gem5/configs/download_check.py" is used by the
"test-resource-downloading" test (defined in
"tests/gem5/gem5-resources/test_download_resources.py" and ran as part
of the "very-long" suite).
Prior to this change "download_check.py" would download each resource,
check it's md5, then at the end of the script remove all the downloaded
resources. This is inefficient on disk space and was causing our
"very-long" suite of tests to require a machines with a lot of disk
space to run.
This change alters 'download_check.py" to remove each resource after the
md5 check. Thus, only one resource is ever downloaded and present at any
given time during the running of this script.
The dailies timed out as they were running the entire directory
of tests due to a wrong variable named being used. In addition,
the names of tests were adjusted to include the matrix type so
the artifacts won't overwrite each other
Change-Id: Iaa1be8e0cfcbf9d64f1a674590bfe2bf1f0dae90
Updates the directories in which tests are run in accordance
with the refactoring of the testing directory
Change-Id: I93f5c5b0236c5180da04deb425ec2ed6804fa003
"tests/gem5/configs/download_check.py" is used by the
"test-resource-downloading" test (defined in
"tests/gem5/gem5-resources/test_download_resources.py" and ran as part
of the "very-long" suite).
Prior to this change "download_check.py" would download each resource,
check it's md5, then at the end of the script remove all the downloaded
resources. This is inefficient on disk space and was causing our
"very-long" suite of tests to require a machines with a lot of disk
space to run.
This change alters 'download_check.py" to remove each resource after the
md5 check. Thus, only one resource is ever downloaded and present at any
given time during the running of this script.
Change-Id: I38fce100ab09f66c256ccddbcb6f29763839ac40
This merges initial support for RVV. Currently, only the simple CPUs are supported.
The decoder stalls for every vsetvl instruction.
In the future, we will implement vsetvl as a control instruction as described in #144
This changeset reorganizes the testing directory within gem5,
removing the bigger config folders, then replacing them with
smaller configs folders within each directory containing only
the scripts necessary for that set of tests. It also changes
the locations of the config scripts used in each set of tests,
and updates the tests accordingly.
Change-Id: I38297d4496f72bd5cf7200471acd5c4d93002b27
This change adds READMEs to each directory within tests/gem5,
with a short description of the test, as well as how to run it.
Change-Id: I574ebcdc837848b52f21e8c0f8856ff09463284b
Since the O3 and Minor CPU models do not support RVV right now as the
implementation stalls the decode until vsetvl instructions are exectued,
this change calls `fatal` if RVV is not explicitly enabled.
It is possible to override this if you explicitly enable RVV in the
config file.
Change-Id: Ia801911141bb2fb2bedcff3e139bf41ba8936085
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
TODOs:
+ vcompress.vm
Change-Id: I86eceae66e90380416fd3be2c10ad616512b5eba
Co-authored-by: Yang Liu <numbksco@gmail.com>
Co-authored-by: Fan Yang <1209202421@qq.com>
Co-authored-by: Jerin Joy <joy@rivosinc.com>
arch-riscv: Add LICENCE to template files
Change-Id: I825e72bffb84cce559d2e4c1fc2246c3b05a1243
* TODOs:
+ Vector Segment Load/Store
+ Vector Fault-only-first Load
Change-Id: I2815c76404e62babab7e9466e4ea33ea87e66e75
Co-authored-by: Yang Liu <numbksco@gmail.com>
Co-authored-by: Fan Yang <1209202421@qq.com>
Co-authored-by: Jerin Joy <joy@rivosinc.com>
Change-Id: I84363164ca327151101e8a1c3d8441a66338c909
Co-authored-by: Yang Liu <numbksco@gmail.com>
Co-authored-by: Fan Yang <1209202421@qq.com>
arch-riscv: Add a todo to fix vsetvl stall on decode
Change-Id: Iafb129648fba89009345f0c0ad3710f773379bf6
This commit add regs and configs for vector extension
* Add 32 vector arch regs as spec defined and 8 internal regs for
uop-based vector implementation.
* Add default vector configs(VLEN = 256, ELEN = 64). These cannot
be changed yet, since the vector implementation has only be tested
with such configs.
* Add disassamble register name v0~v31 and vtmp0~vtmp7.
* Add CSR registers defined in RISCV Vector Spec v1.0.
* Add vector bitfields.
* Add vector operand_types and operands.
Change-Id: I7bbab1ee9e0aa804d6f15ef7b77fac22d4f7212a
Co-authored-by: Yang Liu <numbksco@gmail.com>
Co-authored-by: Fan Yang <1209202421@qq.com>
Co-authored-by: Jerin Joy <joy@rivosinc.com>
arch-riscv: enable rvv flags only for RV64
Change-Id: I6586e322dfd562b598f63a18964d17326c14d4cf
The MMIO trace contains register values for parts of the GPU that are
not modeled in gem5, such as registers related to the graphics core.
Since MI100 and MI200 do not have anything that is not modeled, the
MMIO trace is not needed, therefore it does not need to be used or
checked and the command line option goes away entirely for MI100/200.
Change-Id: I23839db32b1b072bd44c8c977899a99347fc9687
Starting with ROCm 5.4+, MI100 and MI200 make use of the translate
further bit in the page table. This bit enables mixing 4kiB and 2MiB
pages and is functionally equivalent to mixing page sizes using the
PDE.P bit for which gem5 currently has support.
With PDE.P bit set, we stop walking and the page size is equal to the
level in the page table we stopped at. For example, stopping at level
2 would be a 1GiB page, stopping at level 3 would be a 2MiB page.
This assumes most pages are 4kiB.
When the F bit is used, it is assumed most pages are 2MiB and we will
stop walking at the 3rd level of the page table unless the F bit is set.
When the F bit is set, the 2nd level PDE contains a block fragment size
representing the page size of the next PDE in the form of 2^(12+size).
If the next page has the F bit set we continue walking to the 4th level.
The block fragment size is hardcoded to 9 in the driver therefore we
assert that the block fragment size must be 0 or 9.
This enables MI200 with ROCm 5.4+ in gem5. This functionality was
determine by examining the driver source code in Linux and there is no
public documentation about this feature or why the change is made in or
around ROCm 5.4.
Change-Id: I603c0208cd9e821f7ad6eeb1d94ae15eaa146fb9
This SDMA packet is much more common starting around ROCm 5.4.
Previously this was mostly used to clear page tables after an
application ended and was therefore left unimplemented. It is
now used for basic operation like device memsets.
This patch implements constant fill as it is now necessary.
Change-Id: I9b2cf076ec17f5ed07c20bb820e7db0c082bbfbc
When using the new operator, delete should be called
on any allocated memory after it's use is complete.
Change-Id: Id5fcfb264b6ddc252c0a9dcafc2d3b020f7b5019
