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stdlib: stlye fix rv_type to _rvType in isa.hh and isa.cc

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Change-Id: I68e2b1be9150e6528693e68fb73470d158838885
This commit is contained in:
Harshil Patel
2023-08-02 12:25:46 -07:00
parent dceabe5fda
commit 51d492487e
2 changed files with 13 additions and 13 deletions
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18
src/arch/riscv/isa.cc
View File

@@ -244,7 +244,7 @@ RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
} // anonymous namespace
ISA::ISA(const Params &p) :
BaseISA(p), rv_type(p.riscv_type), checkAlignment(p.check_alignment)
BaseISA(p), _rvType(p.riscv_type), checkAlignment(p.check_alignment)
{
_regClasses.push_back(&intRegClass);
_regClasses.push_back(&floatRegClass);
@@ -299,8 +299,8 @@ void ISA::clear()
// mark FS is initial
status.fs = INITIAL;
// rv_type dependent init.
switch (rv_type) {
// _rvType dependent init.
switch (_rvType) {
case RV32:
misa.rv32_mxl = 1;
break;
@@ -309,7 +309,7 @@ void ISA::clear()
status.uxl = status.sxl = 2;
break;
default:
panic("%s: Unknown rv_type: %d", name(), (int)rv_type);
panic("%s: Unknown _rvType: %d", name(), (int)_rvType);
}
miscRegFile[MISCREG_ISA] = misa;
@@ -465,7 +465,7 @@ ISA::readMiscReg(RegIndex idx)
(status.xs == 3) || (status.fs == 3) || (status.vs == 3);
// For RV32, the SD bit is at index 31
// For RV64, the SD bit is at index 63.
switch (rv_type) {
switch (_rvType) {
case RV32:
status.rv32_sd = sd_bit;
break;
@@ -473,7 +473,7 @@ ISA::readMiscReg(RegIndex idx)
status.rv64_sd = sd_bit;
break;
default:
panic("%s: Unknown rv_type: %d", name(), (int)rv_type);
panic("%s: Unknown _rvType: %d", name(), (int)_rvType);
}
setMiscRegNoEffect(idx, status);
@@ -541,7 +541,7 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
assert(readMiscRegNoEffect(MISCREG_PRV) == PRV_M);
int regSize = 0;
switch (rv_type) {
switch (_rvType) {
case RV32:
regSize = 4;
break;
@@ -549,7 +549,7 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
regSize = 8;
break;
default:
panic("%s: Unknown rv_type: %d", name(), (int)rv_type);
panic("%s: Unknown _rvType: %d", name(), (int)_rvType);
}
// Specs do not seem to mention what should be
@@ -643,7 +643,7 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
break;
case MISCREG_STATUS:
{
if (rv_type != RV32) {
if (_rvType != RV32) {
// SXL and UXL are hard-wired to 64 bit
auto cur = readMiscRegNoEffect(idx);
val &= ~(STATUS_SXL_MASK | STATUS_UXL_MASK);

8
src/arch/riscv/isa.hh
View File

@@ -70,7 +70,7 @@ enum FPUStatus
class ISA : public BaseISA
{
protected:
RiscvType rv_type;
RiscvType _rvType;
std::vector<RegVal> miscRegFile;
bool checkAlignment;
@@ -89,7 +89,7 @@ class ISA : public BaseISA
PCStateBase*
newPCState(Addr new_inst_addr=0) const override
{
return new PCState(new_inst_addr, rv_type);
return new PCState(new_inst_addr, _rvType);
}
public:
@@ -110,7 +110,7 @@ class ISA : public BaseISA
virtual const std::unordered_map<int, RegVal>&
getCSRMaskMap() const
{
return CSRMasks[rv_type];
return CSRMasks[_rvType];
}
bool alignmentCheckEnabled() const { return checkAlignment; }
@@ -134,7 +134,7 @@ class ISA : public BaseISA
void resetThread() override;
RiscvType rvType() const { return rv_type; }
RiscvType rvType() const { return _rvType; }
void
clearLoadReservation(ContextID cid)