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arch-riscv: Implemented zicbom/zicboz extensions for RISC V (#137)

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This commit is contained in:
Jason Lowe-Power
2023-08-04 11:39:34 -07:00
committed by GitHub
parent ed44df5d02 14c25a383c
commit 7a9f7f51ae
2 changed files with 24 additions and 0 deletions
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17
src/arch/riscv/isa/decoder.isa
View File

@@ -677,6 +677,23 @@ decode QUADRANT default Unknown::unknown() {
0x1: fence_i({{
}}, uint64_t, IsNonSpeculative, IsSerializeAfter, No_OpClass);
}
0x2: decode FUNCT12 {
format CBMOp {
0x0: cbo_inval({{
Mem = 0;
}}, mem_flags=[INVALIDATE, DST_POC]);
0x1: cbo_clean({{
Mem = 0;
}}, mem_flags=[CLEAN, DST_POC]);
0x2: cbo_flush({{
Mem = 0;
}}, mem_flags=[CLEAN, INVALIDATE, DST_POC]);
0x4: cbo_zero({{
Mem = 0;
}}, mem_flags=[CACHE_BLOCK_ZERO]);
}
}
}
0x04: decode FUNCT3 {

7
src/arch/riscv/isa/formats/mem.isa
View File

@@ -243,3 +243,10 @@ def format Store(memacc_code, ea_code={{EA = rvZext(Rs1 + offset);}},
LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
inst_flags, 'Store', exec_template_base='Store')
}};
def format CBMOp(memacc_code, ea_code={{EA = rvZext(Rs1 + offset);}},
offset_code={{offset = 0;}}, mem_flags=[], inst_flags=[]) {{
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, offset_code, ea_code, memacc_code, mem_flags,
inst_flags, 'Store', exec_template_base='Store')
}};