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arch-riscv: Make vset*vl* instructions serialize

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Current implementation of vset*vl* instructions serialize pipeline and
are non-speculative.

Change-Id: Ibf93b60133fb3340690b126db12827e36e2c202d
This commit is contained in:
Adrià Armejach
2023-08-02 14:05:21 +02:00
parent 98d68a7307
commit 884d62b33a
1 changed files with 5 additions and 3 deletions
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8
src/arch/riscv/isa/decoder.isa
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@@ -4344,7 +4344,7 @@ decode QUADRANT default Unknown::unknown() {
uint64_t requested_vtype = zimm11;
Rd_ud = 0;
}}, VectorConfigOp, IsDirectControl, IsCondControl);
}}, VectorConfigOp, IsSerializeAfter, IsNonSpeculative);
0x1: decode BIT30 {
0x0: vsetvl({{
uint64_t rd_bits = RD;
@@ -4353,7 +4353,8 @@ decode QUADRANT default Unknown::unknown() {
uint64_t requested_vtype = Rs2_ud;
Rd_ud = 0;
}}, VectorConfigOp, IsDirectControl, IsCondControl);
}}, VectorConfigOp, IsSerializeAfter,
IsNonSpeculative);
0x1: vsetivli({{
uint64_t rd_bits = RD;
uint64_t rs1_bits = -1;
@@ -4361,7 +4362,8 @@ decode QUADRANT default Unknown::unknown() {
uint64_t requested_vtype = zimm10;
Rd_ud = 0;
}}, VectorConfigOp, IsDirectControl, IsCondControl);
}}, VectorConfigOp, IsSerializeAfter,
IsNonSpeculative);
}
}
}