From 884d62b33af866664960e399ddc09b654753b794 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Adri=C3=A0=20Armejach?= <adria.armejach@bsc.es>
Date: Wed, 2 Aug 2023 14:05:21 +0200
Subject: [PATCH] arch-riscv: Make vset*vl* instructions serialize

Current implementation of vset*vl* instructions serialize pipeline and
are non-speculative.

Change-Id: Ibf93b60133fb3340690b126db12827e36e2c202d
---
 src/arch/riscv/isa/decoder.isa | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 2b46752ffe..d34adfaa02 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -4344,7 +4344,7 @@ decode QUADRANT default Unknown::unknown() {
                         uint64_t requested_vtype = zimm11;
 
                         Rd_ud = 0;
-                    }}, VectorConfigOp, IsDirectControl, IsCondControl);
+                    }}, VectorConfigOp, IsSerializeAfter, IsNonSpeculative);
                     0x1: decode BIT30 {
                         0x0: vsetvl({{
                             uint64_t rd_bits = RD;
@@ -4353,7 +4353,8 @@ decode QUADRANT default Unknown::unknown() {
                             uint64_t requested_vtype = Rs2_ud;
 
                             Rd_ud = 0;
-                        }}, VectorConfigOp, IsDirectControl, IsCondControl);
+                        }}, VectorConfigOp, IsSerializeAfter,
+                        IsNonSpeculative);
                         0x1: vsetivli({{
                             uint64_t rd_bits = RD;
                             uint64_t rs1_bits = -1;
@@ -4361,7 +4362,8 @@ decode QUADRANT default Unknown::unknown() {
                             uint64_t requested_vtype = zimm10;
 
                             Rd_ud = 0;
-                        }}, VectorConfigOp, IsDirectControl, IsCondControl);
+                        }}, VectorConfigOp, IsSerializeAfter,
+                        IsNonSpeculative);
                     }
                 }
             }