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tests: Update layout of testing directory

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This changeset reorganizes the testing directory within gem5,
removing the bigger config folders, then replacing them with
smaller configs folders within each directory containing only
the scripts necessary for that set of tests. It also changes
the locations of the config scripts used in each set of tests,
and updates the tests accordingly.

Change-Id: I38297d4496f72bd5cf7200471acd5c4d93002b27
This commit is contained in:
Melissa Jost
2023-05-05 10:13:14 -07:00
parent 7ff67459b6
commit 3bf92d0e0b
110 changed files with 883 additions and 2827 deletions
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60
tests/configs/dram-lowp.py
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# Copyright (c) 2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2015 Jason Lowe-Power
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# A wrapper around configs/dram/low_power_sweep.py
# For some reason, this is implicitly needed by run.py
root = None
import m5
def run_test(root):
# Called from tests/run.py
import sys
argv = [
sys.argv[0],
# Add a specific page policy and specify the number of ranks
f"-p{page_policy}",
"-r 2",
]
# Execute the script we are wrapping
run_config("configs/dram/low_power_sweep.py", argv=argv)

164
tests/configs/gpu-randomtest-ruby.py
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#
# Copyright (c) 2010-2015 Advanced Micro Devices, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
from m5.defines import buildEnv
from m5.util import addToPath
import os, argparse, sys
m5.util.addToPath("../configs/")
from ruby import Ruby
from common import Options
parser = argparse.ArgumentParser()
Options.addCommonOptions(parser)
# add the gpu specific options expected by the the gpu and gpu_RfO
parser.add_argument(
"-u",
"--num-compute-units",
type=int,
default=8,
help="number of compute units in the GPU",
)
parser.add_argument(
"--num-cp",
type=int,
default=0,
help="Number of GPU Command Processors (CP)",
)
parser.add_argument(
"--simds-per-cu", type=int, default=4, help="SIMD unitsper CU"
)
parser.add_argument(
"--wf-size", type=int, default=64, help="Wavefront size(in workitems)"
)
parser.add_argument(
"--wfs-per-simd",
type=int,
default=10,
help="Number of WF slots per SIMD",
)
# Add the ruby specific and protocol specific options
Ruby.define_options(parser)
args = parser.parse_args()
#
# Set the default cache size and associativity to be very small to encourage
# races between requests and writebacks.
#
args.l1d_size = "256B"
args.l1i_size = "256B"
args.l2_size = "512B"
args.l3_size = "1kB"
args.l1d_assoc = 2
args.l1i_assoc = 2
args.l2_assoc = 2
args.l3_assoc = 2
args.num_compute_units = 8
args.num_sqc = 2
# Check to for the GPU_RfO protocol. Other GPU protocols are non-SC and will
# not work with the Ruby random tester.
assert buildEnv["PROTOCOL"] == "GPU_RfO"
#
# create the tester and system, including ruby
#
tester = RubyTester(
check_flush=False,
checks_to_complete=100,
wakeup_frequency=10,
num_cpus=args.num_cpus,
)
# We set the testers as cpu for ruby to find the correct clock domains
# for the L1 Objects.
system = System(cpu=tester)
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage=args.sys_voltage)
system.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=system.voltage_domain
)
system.mem_ranges = AddrRange("256MB")
# the ruby tester reuses num_cpus to specify the
# number of cpu ports connected to the tester object, which
# is stored in system.cpu. because there is only ever one
# tester object, num_cpus is not necessarily equal to the
# size of system.cpu
cpu_list = [system.cpu] * args.num_cpus
Ruby.create_system(args, False, system, cpus=cpu_list)
# Create a separate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=system.voltage_domain
)
tester.num_cpus = len(system.ruby._cpu_ports)
#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
#
system.ruby.randomization = True
for ruby_port in system.ruby._cpu_ports:
#
# Tie the ruby tester ports to the ruby cpu read and write ports
#
if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
tester.cpuInstDataPort = ruby_port.in_ports
elif ruby_port.support_data_reqs:
tester.cpuDataPort = ruby_port.in_ports
elif ruby_port.support_inst_reqs:
tester.cpuInstPort = ruby_port.in_ports
# Do not automatically retry stalled Ruby requests
ruby_port.no_retry_on_stall = True
#
# Tell the sequencer this is the ruby tester so that it
# copies the subblock back to the checker
#
ruby_port.using_ruby_tester = True
# -----------------------
# run simulation
# -----------------------
root = Root(full_system=False, system=system)
root.system.mem_mode = "timing"

433
tests/configs/gpu-ruby.py
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#
# Copyright (c) 2015 Advanced Micro Devices, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
from m5.defines import buildEnv
from m5.util import addToPath
import os, argparse, sys, math, glob
m5.util.addToPath("../configs/")
from ruby import Ruby
from common import Options
from common import GPUTLBOptions, GPUTLBConfig
def run_test(root):
"""gpu test requires a specialized run_test implementation to set up the
mmio space."""
# instantiate configuration
m5.instantiate()
# Now that the system has been constructed, setup the mmio space
root.system.cpu[0].workload[0].map(0x10000000, 0x200000000, 4096)
# simulate until program terminates
exit_event = m5.simulate(maxtick)
print("Exiting @ tick", m5.curTick(), "because", exit_event.getCause())
parser = argparse.ArgumentParser()
Options.addCommonOptions(parser)
Options.addSEOptions(parser)
parser.add_argument(
"-k",
"--kernel-files",
help="file(s) containing GPU kernel code (colon separated)",
)
parser.add_argument(
"-u",
"--num-compute-units",
type=int,
default=2,
help="number of GPU compute units",
),
parser.add_argument(
"--num-cp",
type=int,
default=0,
help="Number of GPU Command Processors (CP)",
)
parser.add_argument(
"--simds-per-cu", type=int, default=4, help="SIMD unitsper CU"
)
parser.add_argument(
"--cu-per-sqc",
type=int,
default=4,
help="number of CUssharing an SQC (icache, and thus icache TLB)",
)
parser.add_argument(
"--wf-size", type=int, default=64, help="Wavefront size(in workitems)"
)
parser.add_argument(
"--wfs-per-simd",
type=int,
default=8,
help="Number of WF slots per SIMD",
)
parser.add_argument(
"--sp-bypass-path-length",
type=int,
default=4,
help="Number of stages of bypass path in vector ALU for Single "
"Precision ops",
)
parser.add_argument(
"--dp-bypass-path-length",
type=int,
default=4,
help="Number of stages of bypass path in vector ALU for Double "
"Precision ops",
)
parser.add_argument(
"--issue-period",
type=int,
default=4,
help="Number of cycles per vector instruction issue period",
)
parser.add_argument(
"--glbmem-wr-bus-width",
type=int,
default=32,
help="VGPR to Coalescer (Global Memory) data bus width in bytes",
)
parser.add_argument(
"--glbmem-rd-bus-width",
type=int,
default=32,
help="Coalescer to VGPR (Global Memory) data bus width in bytes",
)
parser.add_argument(
"--shr-mem-pipes-per-cu",
type=int,
default=1,
help="Number of Shared Memory pipelines per CU",
)
parser.add_argument(
"--glb-mem-pipes-per-cu",
type=int,
default=1,
help="Number of Global Memory pipelines per CU",
)
parser.add_argument(
"--vreg-file-size",
type=int,
default=2048,
help="number of physical vector registers per SIMD",
)
parser.add_argument(
"--bw-scalor",
type=int,
default=0,
help="bandwidth scalor for scalability analysis",
)
parser.add_argument("--CPUClock", type=str, default="2GHz", help="CPU clock")
parser.add_argument("--GPUClock", type=str, default="1GHz", help="GPU clock")
parser.add_argument(
"--cpu-voltage",
action="store",
type=str,
default="1.0V",
help="""CPU voltage domain""",
)
parser.add_argument(
"--gpu-voltage",
action="store",
type=str,
default="1.0V",
help="""CPU voltage domain""",
)
parser.add_argument(
"--CUExecPolicy",
type=str,
default="OLDEST-FIRST",
help="WF exec policy (OLDEST-FIRST, ROUND-ROBIN)",
)
parser.add_argument(
"--xact-cas-mode",
action="store_true",
help="enable load_compare mode (transactional CAS)",
)
parser.add_argument(
"--SegFaultDebug",
action="store_true",
help="checks for GPU seg fault before TLB access",
)
parser.add_argument(
"--LocalMemBarrier",
action="store_true",
help="Barrier does not wait for writethroughs to complete",
)
parser.add_argument(
"--countPages",
action="store_true",
help="Count Page Accesses and output in per-CU output files",
)
parser.add_argument("--TLB-prefetch", type=int, help="prefetch depth forTLBs")
parser.add_argument(
"--pf-type",
type=str,
help="type of prefetch: PF_CU, PF_WF, PF_PHASE, PF_STRIDE",
)
parser.add_argument("--pf-stride", type=int, help="set prefetch stride")
parser.add_argument(
"--numLdsBanks",
type=int,
default=32,
help="number of physical banks per LDS module",
)
parser.add_argument(
"--ldsBankConflictPenalty",
type=int,
default=1,
help="number of cycles per LDS bank conflict",
)
# Add the ruby specific and protocol specific options
Ruby.define_options(parser)
GPUTLBOptions.tlb_options(parser)
args = parser.parse_args()
# The GPU cache coherence protocols only work with the backing store
args.access_backing_store = True
# Currently, the sqc (I-Cache of GPU) is shared by
# multiple compute units(CUs). The protocol works just fine
# even if sqc is not shared. Overriding this option here
# so that the user need not explicitly set this (assuming
# sharing sqc is the common usage)
n_cu = args.num_compute_units
num_sqc = int(math.ceil(float(n_cu) / args.cu_per_sqc))
args.num_sqc = num_sqc # pass this to Ruby
########################## Creating the GPU system ########################
# shader is the GPU
shader = Shader(
n_wf=args.wfs_per_simd,
clk_domain=SrcClockDomain(
clock=args.GPUClock,
voltage_domain=VoltageDomain(voltage=args.gpu_voltage),
),
timing=True,
)
# GPU_RfO(Read For Ownership) implements SC/TSO memory model.
# Other GPU protocols implement release consistency at GPU side.
# So, all GPU protocols other than GPU_RfO should make their writes
# visible to the global memory and should read from global memory
# during kernal boundary. The pipeline initiates(or do not initiate)
# the acquire/release operation depending on this impl_kern_boundary_sync
# flag. This flag=true means pipeline initiates a acquire/release operation
# at kernel boundary.
if buildEnv["PROTOCOL"] == "GPU_RfO":
shader.impl_kern_boundary_sync = False
else:
shader.impl_kern_boundary_sync = True
# Switching off per-lane TLB by default
per_lane = False
if args.TLB_config == "perLane":
per_lane = True
# List of compute units; one GPU can have multiple compute units
compute_units = []
for i in range(n_cu):
compute_units.append(
ComputeUnit(
cu_id=i,
perLaneTLB=per_lane,
num_SIMDs=args.simds_per_cu,
wfSize=args.wf_size,
spbypass_pipe_length=args.sp_bypass_path_length,
dpbypass_pipe_length=args.dp_bypass_path_length,
issue_period=args.issue_period,
coalescer_to_vrf_bus_width=args.glbmem_rd_bus_width,
vrf_to_coalescer_bus_width=args.glbmem_wr_bus_width,
num_global_mem_pipes=args.glb_mem_pipes_per_cu,
num_shared_mem_pipes=args.shr_mem_pipes_per_cu,
n_wf=args.wfs_per_simd,
execPolicy=args.CUExecPolicy,
xactCasMode=args.xact_cas_mode,
debugSegFault=args.SegFaultDebug,
functionalTLB=True,
localMemBarrier=args.LocalMemBarrier,
countPages=args.countPages,
localDataStore=LdsState(
banks=args.numLdsBanks,
bankConflictPenalty=args.ldsBankConflictPenalty,
),
)
)
wavefronts = []
vrfs = []
for j in range(args.simds_per_cu):
for k in range(int(shader.n_wf)):
wavefronts.append(Wavefront(simdId=j, wf_slot_id=k))
vrfs.append(
VectorRegisterFile(
simd_id=j, num_regs_per_simd=args.vreg_file_size
)
)
compute_units[-1].wavefronts = wavefronts
compute_units[-1].vector_register_file = vrfs
if args.TLB_prefetch:
compute_units[-1].prefetch_depth = args.TLB_prefetch
compute_units[-1].prefetch_prev_type = args.pf_type
# attach the LDS and the CU to the bus (actually a Bridge)
compute_units[-1].ldsPort = compute_units[-1].ldsBus.slave
compute_units[-1].ldsBus.master = compute_units[-1].localDataStore.cuPort
# Attach compute units to GPU
shader.CUs = compute_units
# this is a uniprocessor only test, thus the shader is the second index in the
# list of "system.cpus"
args.num_cpus = 1
shader_idx = 1
cpu = TimingSimpleCPU(cpu_id=0)
########################## Creating the GPU dispatcher ########################
# Dispatcher dispatches work from host CPU to GPU
host_cpu = cpu
dispatcher = GpuDispatcher()
# Currently does not test for command processors
cpu_list = [cpu] + [shader] + [dispatcher]
system = System(
cpu=cpu_list,
mem_ranges=[AddrRange(args.mem_size)],
mem_mode="timing",
workload=SEWorkload(),
)
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage=args.sys_voltage)
system.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=system.voltage_domain
)
# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu[0].clk_domain = SrcClockDomain(
clock="2GHz", voltage_domain=system.voltage_domain
)
# configure the TLB hierarchy
GPUTLBConfig.config_tlb_hierarchy(args, system, shader_idx)
# create Ruby system
system.piobus = IOXBar(
width=32, response_latency=0, frontend_latency=0, forward_latency=0
)
Ruby.create_system(args, None, system)
# Create a separate clock for Ruby
system.ruby.clk_domain = SrcClockDomain(
clock=args.ruby_clock, voltage_domain=system.voltage_domain
)
# create the interrupt controller
cpu.createInterruptController()
#
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
cpu.connectAllPorts(
system.ruby._cpu_ports[0].in_ports,
system.ruby._cpu_ports[0].in_ports,
system.ruby._cpu_ports[0].interrupt_out_port,
)
system.ruby._cpu_ports[0].mem_request_port = system.piobus.cpu_side_ports
# attach CU ports to Ruby
# Because of the peculiarities of the CP core, you may have 1 CPU but 2
# sequencers and thus 2 _cpu_ports created. Your GPUs shouldn't be
# hooked up until after the CP. To make this script generic, figure out
# the index as below, but note that this assumes there is one sequencer
# per compute unit and one sequencer per SQC for the math to work out
# correctly.
gpu_port_idx = (
len(system.ruby._cpu_ports) - args.num_compute_units - args.num_sqc
)
gpu_port_idx = gpu_port_idx - args.num_cp * 2
wavefront_size = args.wf_size
for i in range(n_cu):
# The pipeline issues wavefront_size number of uncoalesced requests
# in one GPU issue cycle. Hence wavefront_size mem ports.
for j in range(wavefront_size):
system.cpu[shader_idx].CUs[i].memory_port[j] = system.ruby._cpu_ports[
gpu_port_idx
].slave[j]
gpu_port_idx += 1
for i in range(n_cu):
if i > 0 and not i % args.cu_per_sqc:
gpu_port_idx += 1
system.cpu[shader_idx].CUs[i].sqc_port = system.ruby._cpu_ports[
gpu_port_idx
].slave
gpu_port_idx = gpu_port_idx + 1
# Current regression tests do not support the command processor
assert args.num_cp == 0
# connect dispatcher to the system.piobus
dispatcher.pio = system.piobus.mem_side_ports
dispatcher.dma = system.piobus.cpu_side_ports
################# Connect the CPU and GPU via GPU Dispatcher ###################
# CPU rings the GPU doorbell to notify a pending task
# using this interface.
# And GPU uses this interface to notify the CPU of task completion
# The communcation happens through emulated driver.
# Note this implicit setting of the cpu_pointer, shader_pointer and tlb array
# parameters must be after the explicit setting of the System cpu list
shader.cpu_pointer = host_cpu
dispatcher.cpu = host_cpu
dispatcher.shader_pointer = shader
# -----------------------
# run simulation
# -----------------------
root = Root(full_system=False, system=system)
m5.ticks.setGlobalFrequency("1THz")
root.system.mem_mode = "timing"

60
tests/configs/memcheck.py
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@@ -1,60 +0,0 @@
# Copyright (c) 2016 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2015 Jason Lowe-Power
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
# the traffic generator is only available if we have protobuf support,
# so potentially skip this test
require_sim_object("TrafficGen")
# A wrapper around configs/example/memcheck.py
# For some reason, this is implicitly needed by run.py
root = None
def run_test(root):
# Called from tests/run.py
import sys
argv = [sys.argv[0], "-m %d" % maxtick]
# Execute the script we are wrapping
run_config("configs/example/memcheck.py", argv=argv)

83
tests/configs/memtest-filter.py
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@@ -1,83 +0,0 @@
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
m5.util.addToPath("../configs/")
from common.Caches import *
# MAX CORES IS 8 with the fals sharing method
nb_cores = 8
cpus = [MemTest() for i in range(nb_cores)]
# system simulated
system = System(
cpu=cpus,
physmem=SimpleMemory(),
membus=SystemXBar(width=16, snoop_filter=SnoopFilter()),
)
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain()
system.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=system.voltage_domain
)
# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu_clk_domain = SrcClockDomain(
clock="2GHz", voltage_domain=system.voltage_domain
)
system.toL2Bus = L2XBar(
clk_domain=system.cpu_clk_domain, snoop_filter=SnoopFilter()
)
system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, size="64kB", assoc=8)
system.l2c.cpu_side = system.toL2Bus.mem_side_ports
# connect l2c to membus
system.l2c.mem_side = system.membus.cpu_side_ports
# add L1 caches
for cpu in cpus:
# All cpus are associated with cpu_clk_domain
cpu.clk_domain = system.cpu_clk_domain
cpu.l1c = L1Cache(size="32kB", assoc=4)
cpu.l1c.cpu_side = cpu.port
cpu.l1c.mem_side = system.toL2Bus.cpu_side_ports
system.system_port = system.membus.cpu_side_ports
# connect memory to membus
system.physmem.port = system.membus.mem_side_ports
# -----------------------
# run simulation
# -----------------------
root = Root(full_system=False, system=system)
root.system.mem_mode = "timing"

122
tests/configs/memtest-ruby.py
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@@ -1,122 +0,0 @@
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# Copyright (c) 2010 Advanced Micro Devices, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
from m5.defines import buildEnv
from m5.util import addToPath
import os, argparse, sys
m5.util.addToPath("../configs/")
from ruby import Ruby
from common import Options
parser = argparse.ArgumentParser()
Options.addCommonOptions(parser)
# Add the ruby specific and protocol specific options
Ruby.define_options(parser)
args = parser.parse_args()
#
# Set the default cache size and associativity to be very small to encourage
# races between requests and writebacks.
#
args.l1d_size = "256B"
args.l1i_size = "256B"
args.l2_size = "512B"
args.l3_size = "1kB"
args.l1d_assoc = 2
args.l1i_assoc = 2
args.l2_assoc = 2
args.l3_assoc = 2
args.ports = 32
# MAX CORES IS 8 with the fals sharing method
nb_cores = 8
# ruby does not support atomic, functional, or uncacheable accesses
cpus = [
MemTest(
percent_functional=50, percent_uncacheable=0, suppress_func_errors=True
)
for i in range(nb_cores)
]
# overwrite args.num_cpus with the nb_cores value
args.num_cpus = nb_cores
# system simulated
system = System(cpu=cpus)
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain()
system.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=system.voltage_domain
)
# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu_clk_domain = SrcClockDomain(
clock="2GHz", voltage_domain=system.voltage_domain
)
# All cpus are associated with cpu_clk_domain
for cpu in cpus:
cpu.clk_domain = system.cpu_clk_domain
system.mem_ranges = AddrRange("256MB")
Ruby.create_system(args, False, system)
# Create a separate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(
clock=args.ruby_clock, voltage_domain=system.voltage_domain
)
assert len(cpus) == len(system.ruby._cpu_ports)
for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
#
# Tie the cpu port to the ruby cpu ports and
# physmem, respectively
#
cpus[i].port = ruby_port.in_ports
#
# Since the memtester is incredibly bursty, increase the deadlock
# threshold to 1 million cycles
#
ruby_port.deadlock_threshold = 1000000
# -----------------------
# run simulation
# -----------------------
root = Root(full_system=False, system=system)
root.system.mem_mode = "timing"

77
tests/configs/memtest.py
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@@ -1,77 +0,0 @@
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
m5.util.addToPath("../configs/")
from common.Caches import *
# MAX CORES IS 8 with the fals sharing method
nb_cores = 8
cpus = [MemTest() for i in range(nb_cores)]
# system simulated
system = System(cpu=cpus, physmem=SimpleMemory(), membus=SystemXBar())
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain()
system.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=system.voltage_domain
)
# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu_clk_domain = SrcClockDomain(
clock="2GHz", voltage_domain=system.voltage_domain
)
system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain)
system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, size="64kB", assoc=8)
system.l2c.cpu_side = system.toL2Bus.mem_side_ports
# connect l2c to membus
system.l2c.mem_side = system.membus.cpu_side_ports
# add L1 caches
for cpu in cpus:
# All cpus are associated with cpu_clk_domain
cpu.clk_domain = system.cpu_clk_domain
cpu.l1c = L1Cache(size="32kB", assoc=4)
cpu.l1c.cpu_side = cpu.port
cpu.l1c.mem_side = system.toL2Bus.cpu_side_ports
system.system_port = system.membus.cpu_side_ports
# connect memory to membus
system.physmem.port = system.membus.mem_side_ports
# -----------------------
# run simulation
# -----------------------
root = Root(full_system=False, system=system)
root.system.mem_mode = "timing"

48
tests/configs/minor-timing-mp.py
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@@ -1,48 +0,0 @@
# Copyright (c) 2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from base_config import *
nb_cores = 4
root = BaseSESystem(
mem_mode="timing",
mem_class=DDR3_1600_8x8,
cpu_class=MinorCPU,
num_cpus=nb_cores,
).create_root()

44
tests/configs/minor-timing.py
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@@ -1,44 +0,0 @@
# Copyright (c) 2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from base_config import *
root = BaseSESystemUniprocessor(
mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=MinorCPU
).create_root()

44
tests/configs/o3-timing-checker.py
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@@ -1,44 +0,0 @@
# Copyright (c) 2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from base_config import *
root = BaseSESystemUniprocessor(
mem_mode="timing",
mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU,
checker=True,
).create_root()

68
tests/configs/o3-timing-mp-ruby.py
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@@ -1,68 +0,0 @@
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
nb_cores = 4
cpus = [DerivO3CPU(cpu_id=i) for i in range(nb_cores)]
import ruby_config
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated
system = System(
cpu=cpus,
physmem=ruby_memory,
membus=SystemXBar(),
mem_mode="timing",
clk_domain=SrcClockDomain(clock="1GHz"),
)
# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu_clk_domain = SrcClockDomain(clock="2GHz")
for cpu in cpus:
# create the interrupt controller
cpu.createInterruptController()
cpu.connectBus(system.membus)
# All cpus are associated with cpu_clk_domain
cpu.clk_domain = system.cpu_clk_domain
# connect memory to membus
system.physmem.port = system.membus.mem_side_ports
# Connect the system port for loading of binaries etc
system.system_port = system.membus.cpu_side_ports
# -----------------------
# run simulation
# -----------------------
root = Root(full_system=False, system=system)
root.system.mem_mode = "timing"

48
tests/configs/o3-timing-mp.py
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@@ -1,48 +0,0 @@
# Copyright (c) 2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from base_config import *
nb_cores = 4
root = BaseSESystem(
mem_mode="timing",
mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU,
num_cpus=nb_cores,
).create_root()

63
tests/configs/o3-timing-mt.py
View File

@@ -1,63 +0,0 @@
# Copyright (c) 2013, 2015 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from m5.defines import buildEnv
from base_config import *
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
# If we are running ARM regressions, use a more sensible CPU
# configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
if get_runtime_isa() == ISA.ARM:
root = ArmSESystemUniprocessor(
mem_mode="timing",
mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3,
num_threads=2,
).create_root()
else:
root = BaseSESystemUniprocessor(
mem_mode="timing",
mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU,
num_threads=2,
).create_root()

56
tests/configs/o3-timing-ruby.py
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@@ -1,56 +0,0 @@
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
import ruby_config
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
cpu = DerivO3CPU(cpu_id=0)
system = System(
cpu=cpu,
physmem=ruby_memory,
membus=SystemXBar(),
mem_mode="timing",
clk_domain=SrcClockDomain(clock="1GHz"),
)
# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu.clk_domain = SrcClockDomain(clock="2GHz")
system.physmem.port = system.membus.mem_side_ports
# create the interrupt controller
cpu.createInterruptController()
cpu.connectBus(system.membus)
# Connect the system port for loading of binaries etc
system.system_port = system.membus.cpu_side_ports
root = Root(full_system=False, system=system)

57
tests/configs/o3-timing.py
View File

@@ -1,57 +0,0 @@
# Copyright (c) 2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from m5.defines import buildEnv
from base_config import *
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
# If we are running ARM regressions, use a more sensible CPU
# configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
if get_runtime_isa() == ISA.ARM:
root = ArmSESystemUniprocessor(
mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=O3_ARM_v7a_3
).create_root()
else:
root = BaseSESystemUniprocessor(
mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=DerivO3CPU
).create_root()

41
tests/configs/pc-o3-timing.py
View File

@@ -1,41 +0,0 @@
# Copyright (c) 2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from x86_generic import *
root = LinuxX86FSSystemUniprocessor(
mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=DerivO3CPU
).create_root()

41
tests/configs/pc-simple-atomic.py
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@@ -1,41 +0,0 @@
# Copyright (c) 2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from x86_generic import *
root = LinuxX86FSSystemUniprocessor(
mem_mode="atomic", mem_class=SimpleMemory, cpu_class=AtomicSimpleCPU
).create_root()

91
tests/configs/pc-simple-timing-ruby.py
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@@ -1,91 +0,0 @@
# Copyright (c) 2012 Mark D. Hill and David A. Wood
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5, os, argparse, sys
from m5.objects import *
m5.util.addToPath("../configs/")
from common.Benchmarks import SysConfig
from common import FSConfig, SysPaths
from ruby import Ruby
from common import Options
# Add the ruby specific and protocol specific options
parser = argparse.ArgumentParser()
Options.addCommonOptions(parser)
Ruby.define_options(parser)
args = parser.parse_args()
# Set the default cache size and associativity to be very small to encourage
# races between requests and writebacks.
args.l1d_size = "32kB"
args.l1i_size = "32kB"
args.l2_size = "4MB"
args.l1d_assoc = 2
args.l1i_assoc = 2
args.l2_assoc = 2
args.num_cpus = 2
# the system
mdesc = SysConfig(disks=["linux-x86.img"])
system = FSConfig.makeLinuxX86System(
"timing", args.num_cpus, mdesc=mdesc, Ruby=True
)
system.kernel = SysPaths.binary("x86_64-vmlinux-2.6.22.9")
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage=args.sys_voltage)
system.kernel = FSConfig.binary("x86_64-vmlinux-2.6.22.9.smp")
system.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=system.voltage_domain
)
system.cpu_clk_domain = SrcClockDomain(
clock="2GHz", voltage_domain=system.voltage_domain
)
system.cpu = [
TimingSimpleCPU(cpu_id=i, clk_domain=system.cpu_clk_domain)
for i in range(args.num_cpus)
]
Ruby.create_system(args, True, system, system.iobus, system._dma_ports)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(
clock=args.ruby_clock, voltage_domain=system.voltage_domain
)
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
system.iobus.mem_side_ports = system.ruby._io_port.in_ports
for (i, cpu) in enumerate(system.cpu):
# create the interrupt controller
cpu.createInterruptController()
# Tie the cpu ports to the correct ruby system ports
system.ruby._cpu_ports[i].connectCpuPorts(cpu)
root = Root(full_system=True, system=system)
m5.ticks.setGlobalFrequency("1THz")

41
tests/configs/pc-simple-timing.py
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@@ -1,41 +0,0 @@
# Copyright (c) 2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from x86_generic import *
root = LinuxX86FSSystemUniprocessor(
mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=TimingSimpleCPU
).create_root()

48
tests/configs/pc-switcheroo-full.py
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@@ -1,48 +0,0 @@
# Copyright (c) 2012 ARM Limited
# Copyright (c) 2013 Mark D. Hill and David A. Wood
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from x86_generic import *
import switcheroo
root = LinuxX86FSSwitcheroo(
mem_class=DDR3_1600_8x8,
cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU),
).create_root()
# Setup a custom test method that uses the switcheroo tester that
# switches between CPU models.
run_test = switcheroo.run_test

136
tests/configs/rubytest-ruby.py
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@@ -1,136 +0,0 @@
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# Copyright (c) 2009 Advanced Micro Devices, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
from m5.defines import buildEnv
from m5.util import addToPath
import os, argparse, sys
m5.util.addToPath("../configs/")
from ruby import Ruby
from common import Options
parser = argparse.ArgumentParser()
Options.addNoISAOptions(parser)
# Add the ruby specific and protocol specific options
Ruby.define_options(parser)
args = parser.parse_args()
#
# Set the default cache size and associativity to be very small to encourage
# races between requests and writebacks.
#
args.l1d_size = "256B"
args.l1i_size = "256B"
args.l2_size = "512B"
args.l3_size = "1kB"
args.l1d_assoc = 2
args.l1i_assoc = 2
args.l2_assoc = 2
args.l3_assoc = 2
args.ports = 32
# Turn on flush check for the hammer protocol
check_flush = False
if buildEnv["PROTOCOL"] == "MOESI_hammer":
check_flush = True
#
# create the tester and system, including ruby
#
tester = RubyTester(
check_flush=check_flush,
checks_to_complete=100,
wakeup_frequency=10,
num_cpus=args.num_cpus,
)
# We set the testers as cpu for ruby to find the correct clock domains
# for the L1 Objects.
system = System(cpu=tester)
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage=args.sys_voltage)
system.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=system.voltage_domain
)
system.mem_ranges = AddrRange("256MB")
# the ruby tester reuses num_cpus to specify the
# number of cpu ports connected to the tester object, which
# is stored in system.cpu. because there is only ever one
# tester object, num_cpus is not necessarily equal to the
# size of system.cpu
cpu_list = [system.cpu] * args.num_cpus
Ruby.create_system(args, False, system, cpus=cpu_list)
# Create a separate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=system.voltage_domain
)
assert args.num_cpus == len(system.ruby._cpu_ports)
tester.num_cpus = len(system.ruby._cpu_ports)
#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
#
system.ruby.randomization = True
for ruby_port in system.ruby._cpu_ports:
#
# Tie the ruby tester ports to the ruby cpu read and write ports
#
if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
tester.cpuInstDataPort = ruby_port.in_ports
elif ruby_port.support_data_reqs:
tester.cpuDataPort = ruby_port.in_ports
elif ruby_port.support_inst_reqs:
tester.cpuInstPort = ruby_port.in_ports
# Do not automatically retry stalled Ruby requests
ruby_port.no_retry_on_stall = True
#
# Tell the sequencer this is the ruby tester so that it
# copies the subblock back to the checker
#
ruby_port.using_ruby_tester = True
# -----------------------
# run simulation
# -----------------------
root = Root(full_system=False, system=system)
root.system.mem_mode = "timing"

41
tests/configs/simple-atomic-dummychecker.py
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@@ -1,41 +0,0 @@
# Copyright (c) 2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from base_config import *
root = BaseSESystemUniprocessor(
mem_mode="atomic", cpu_class=AtomicSimpleCPU, checker=True
).create_root()

66
tests/configs/simple-atomic-mp-ruby.py
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@@ -1,66 +0,0 @@
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
nb_cores = 4
cpus = [AtomicSimpleCPU(cpu_id=i) for i in range(nb_cores)]
import ruby_config
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated
system = System(
cpu=cpus,
physmem=ruby_memory,
membus=SystemXBar(),
clk_domain=SrcClockDomain(clock="1GHz"),
)
# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu.clk_domain = SrcClockDomain(clock="2GHz")
# add L1 caches
for cpu in cpus:
cpu.connectBus(system.membus)
# All cpus are associated with cpu_clk_domain
cpu.clk_domain = system.cpu_clk_domain
# connect memory to membus
system.physmem.port = system.membus.mem_side_ports
# Connect the system port for loading of binaries etc
system.system_port = system.membus.cpu_side_ports
# -----------------------
# run simulation
# -----------------------
root = Root(full_system=False, system=system)
root.system.mem_mode = "atomic"

45
tests/configs/simple-atomic-mp.py
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@@ -1,45 +0,0 @@
# Copyright (c) 2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from base_config import *
nb_cores = 4
root = BaseSESystem(
mem_mode="atomic", cpu_class=AtomicSimpleCPU, num_cpus=nb_cores
).create_root()

44
tests/configs/simple-atomic.py
View File

@@ -1,44 +0,0 @@
# Copyright (c) 2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from base_config import *
root = BaseSESystemUniprocessor(
mem_mode="atomic", cpu_class=AtomicSimpleCPU
).create_root()

97
tests/configs/simple-timing-mp-ruby.py
View File

@@ -1,97 +0,0 @@
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
from m5.defines import buildEnv
from m5.util import addToPath
import os, argparse, sys
m5.util.addToPath("../configs/")
from common import Options
from ruby import Ruby
parser = argparse.ArgumentParser()
Options.addCommonOptions(parser)
# Add the ruby specific and protocol specific options
Ruby.define_options(parser)
args = parser.parse_args()
#
# Set the default cache size and associativity to be very small to encourage
# races between requests and writebacks.
#
args.l1d_size = "256B"
args.l1i_size = "256B"
args.l2_size = "512B"
args.l3_size = "1kB"
args.l1d_assoc = 2
args.l1i_assoc = 2
args.l2_assoc = 2
args.l3_assoc = 2
nb_cores = 4
cpus = [TimingSimpleCPU(cpu_id=i) for i in range(nb_cores)]
# overwrite the num_cpus to equal nb_cores
args.num_cpus = nb_cores
# system simulated
system = System(cpu=cpus, clk_domain=SrcClockDomain(clock="1GHz"))
# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu.clk_domain = SrcClockDomain(clock="2GHz")
Ruby.create_system(args, False, system)
# Create a separate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock=args.ruby_clock)
assert args.num_cpus == len(system.ruby._cpu_ports)
for (i, cpu) in enumerate(system.cpu):
# create the interrupt controller
cpu.createInterruptController()
#
# Tie the cpu ports to the ruby cpu ports
#
cpu.connectAllPorts(
system.ruby._cpu_ports[i].in_ports,
system.ruby._cpu_ports[i].in_ports,
system.ruby._cpu_ports[i].interrupt_out_port,
)
# -----------------------
# run simulation
# -----------------------
root = Root(full_system=False, system=system)
root.system.mem_mode = "timing"

45
tests/configs/simple-timing-mp.py
View File

@@ -1,45 +0,0 @@
# Copyright (c) 2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from base_config import *
nb_cores = 4
root = BaseSESystem(
mem_mode="timing", cpu_class=TimingSimpleCPU, num_cpus=nb_cores
).create_root()

104
tests/configs/simple-timing-ruby.py
View File

@@ -1,104 +0,0 @@
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
from m5.defines import buildEnv
from m5.util import addToPath
import os, argparse, sys
m5.util.addToPath("../configs/")
from ruby import Ruby
from common import Options
parser = argparse.ArgumentParser()
Options.addCommonOptions(parser)
# Add the ruby specific and protocol specific options
Ruby.define_options(parser)
args = parser.parse_args()
#
# Set the default cache size and associativity to be very small to encourage
# races between requests and writebacks.
#
args.l1d_size = "256B"
args.l1i_size = "256B"
args.l2_size = "512B"
args.l3_size = "1kB"
args.l1d_assoc = 2
args.l1i_assoc = 2
args.l2_assoc = 2
args.l3_assoc = 2
# this is a uniprocessor only test
args.num_cpus = 1
cpu = TimingSimpleCPU(cpu_id=0)
system = System(cpu=cpu)
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage=args.sys_voltage)
system.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=system.voltage_domain
)
# Create a seperate clock domain for components that should run at
# CPUs frequency
system.cpu.clk_domain = SrcClockDomain(
clock="2GHz", voltage_domain=system.voltage_domain
)
system.mem_ranges = AddrRange("256MB")
Ruby.create_system(args, False, system)
# Create a separate clock for Ruby
system.ruby.clk_domain = SrcClockDomain(
clock=args.ruby_clock, voltage_domain=system.voltage_domain
)
assert len(system.ruby._cpu_ports) == 1
# create the interrupt controller
cpu.createInterruptController()
#
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
cpu.connectAllPorts(
system.ruby._cpu_ports[0].in_ports,
system.ruby._cpu_ports[0].in_ports,
system.ruby._cpu_ports[0].interrupt_out_port,
)
# -----------------------
# run simulation
# -----------------------
root = Root(full_system=False, system=system)
root.system.mem_mode = "timing"

44
tests/configs/simple-timing.py
View File

@@ -1,44 +0,0 @@
# Copyright (c) 2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from base_config import *
root = BaseSESystemUniprocessor(
mem_mode="timing", cpu_class=TimingSimpleCPU
).create_root()

59
tests/configs/t1000-simple-atomic.py
View File

@@ -1,59 +0,0 @@
# Copyright (c) 2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
m5.util.addToPath("../configs/")
from common import FSConfig
try:
system = FSConfig.makeSparcSystem("atomic")
except IOError as e:
skip_test(reason=str(e))
system.voltage_domain = VoltageDomain()
system.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=system.voltage_domain
)
system.cpu_clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=system.voltage_domain
)
cpu = AtomicSimpleCPU(cpu_id=0, clk_domain=system.cpu_clk_domain)
system.cpu = cpu
# create the interrupt controller
cpu.createInterruptController()
cpu.connectBus(system.membus)
# create the memory controllers and connect them, stick with
# the physmem name to avoid bumping all the reference stats
system.physmem = [SimpleMemory(range=r) for r in system.mem_ranges]
for i in range(len(system.physmem)):
system.physmem[i].port = system.membus.mem_side_ports
root = Root(full_system=True, system=system)
m5.ticks.setGlobalFrequency("2GHz")

123
tests/configs/x86_generic.py
View File

@@ -1,123 +0,0 @@
# Copyright (c) 2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from abc import ABCMeta, abstractmethod
import m5
from m5.objects import *
from m5.proxy import *
m5.util.addToPath("../configs/")
from common.Benchmarks import SysConfig
from common import FSConfig, SysPaths
from common.Caches import *
from base_config import *
class LinuxX86SystemBuilder(object):
"""Mix-in that implements create_system.
This mix-in is intended as a convenient way of adding an
X86-specific create_system method to a class deriving from one of
the generic base systems.
"""
def __init__(self):
pass
def create_system(self):
mdesc = SysConfig(disks=["linux-x86.img"])
system = FSConfig.makeLinuxX86System(
self.mem_mode, numCPUs=self.num_cpus, mdesc=mdesc
)
system.kernel = SysPaths.binary("x86_64-vmlinux-2.6.22.9")
self.init_system(system)
return system
class LinuxX86FSSystem(LinuxX86SystemBuilder, BaseFSSystem):
"""Basic X86 full system builder."""
def __init__(self, **kwargs):
"""Initialize an X86 system that supports full system simulation.
Note: Keyword arguments that are not listed below will be
passed to the BaseFSSystem.
Keyword Arguments:
machine_type -- String describing the platform to simulate
"""
BaseSystem.__init__(self, **kwargs)
LinuxX86SystemBuilder.__init__(self)
def create_caches_private(self, cpu):
cpu.addPrivateSplitL1Caches(
L1_ICache(size="32kB", assoc=1),
L1_DCache(size="32kB", assoc=4),
PageTableWalkerCache(),
PageTableWalkerCache(),
)
class LinuxX86FSSystemUniprocessor(
LinuxX86SystemBuilder, BaseFSSystemUniprocessor
):
"""Basic X86 full system builder for uniprocessor systems.
Note: This class is a specialization of the X86FSSystem and is
only really needed to provide backwards compatibility for existing
test cases.
"""
def __init__(self, **kwargs):
BaseFSSystemUniprocessor.__init__(self, **kwargs)
LinuxX86SystemBuilder.__init__(self)
def create_caches_private(self, cpu):
cpu.addTwoLevelCacheHierarchy(
L1_ICache(size="32kB", assoc=1),
L1_DCache(size="32kB", assoc=4),
L2Cache(size="4MB", assoc=8),
PageTableWalkerCache(),
PageTableWalkerCache(),
)
class LinuxX86FSSwitcheroo(LinuxX86SystemBuilder, BaseFSSwitcheroo):
"""Uniprocessor X86 system prepared for CPU switching"""
def __init__(self, **kwargs):
BaseFSSwitcheroo.__init__(self, **kwargs)
LinuxX86SystemBuilder.__init__(self)

0
tests/gem5/configs/arm_boot_exit_run.py → tests/gem5/arm_boot_tests/configs/arm_boot_exit_run.py
View File

3
tests/gem5/arm_boot_tests/test_linux_boot.py
View File

@@ -46,7 +46,7 @@ def test_boot(
):
name = f"{cpu}-cpu_{num_cpus}-cores_{mem_system}_{memory_class}_\
arm-boot-test"
arm_boot_test"
verifiers = []
@@ -90,6 +90,7 @@ arm-boot-test"
config.base_dir,
"tests",
"gem5",
"arm_boot_tests",
"configs",
"arm_boot_exit_run.py",
),

184
tests/gem5/asmtest/configs/simple_binary_run.py Normal file
View File

@@ -0,0 +1,184 @@
# Copyright (c) 2021 The Regents of the University of California
# Copyright (c) 2022 Google Inc
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
"""
A run script for a very simple Syscall-Execution running simple binaries.
The system has no cache heirarchy and is as "bare-bones" as you can get in
gem5 while still being functinal.
"""
from gem5.resources.resource import Resource
from gem5.components.processors.cpu_types import (
get_cpu_types_str_set,
get_cpu_type_from_str,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.boards.mem_mode import MemMode
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
from gem5.isas import get_isa_from_str, get_isas_str_set, ISA
from m5.util import fatal
import argparse
import importlib
cpu_types_string_map = {
CPUTypes.ATOMIC: "AtomicSimpleCPU",
CPUTypes.O3: "O3CPU",
CPUTypes.TIMING: "TimingSimpleCPU",
CPUTypes.KVM: "KvmCPU",
CPUTypes.MINOR: "MinorCPU",
}
parser = argparse.ArgumentParser(
description="A gem5 script for running simple binaries in SE mode."
)
parser.add_argument(
"resource", type=str, help="The gem5 resource binary to run."
)
parser.add_argument(
"cpu", type=str, choices=get_cpu_types_str_set(), help="The CPU type used."
)
parser.add_argument(
"isa", type=str, choices=get_isas_str_set(), help="The ISA used"
)
parser.add_argument(
"-b",
"--base-cpu-processor",
action="store_true",
help="Use the BaseCPUProcessor instead of the SimpleProcessor.",
)
parser.add_argument(
"--riscv-32bits",
action="store_true",
help="Use 32 bits core of Riscv CPU",
)
parser.add_argument(
"-r",
"--resource-directory",
type=str,
required=False,
help="The directory in which resources will be downloaded or exist.",
)
parser.add_argument(
"--arguments",
type=str,
action="append",
default=[],
required=False,
help="The input arguments for the binary.",
)
parser.add_argument(
"-n",
"--num-cores",
type=int,
default=1,
required=False,
help="The number of CPU cores to run.",
)
args = parser.parse_args()
# Setup the system.
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600()
isa_enum = get_isa_from_str(args.isa)
cpu_enum = get_cpu_type_from_str(args.cpu)
if isa_enum == ISA.RISCV and args.riscv_32bits and not args.base_cpu_processor:
fatal("To use Riscv 32 CPU, the base_cpu_processor must be specify!")
if args.base_cpu_processor:
if isa_enum == ISA.RISCV and args.riscv_32bits:
m5_objects = importlib.import_module("m5.objects")
cpu_class = getattr(
m5_objects, f"Riscv32{cpu_types_string_map[cpu_enum]}"
)
cores = [
BaseCPUCore(core=cpu_class(cpu_id=i), isa=isa_enum)
for i in range(args.num_cores)
]
else:
cores = [
BaseCPUCore(
core=SimpleCore.cpu_simobject_factory(
cpu_type=cpu_enum,
isa=isa_enum,
core_id=i,
),
isa=isa_enum,
)
for i in range(args.num_cores)
]
processor = BaseCPUProcessor(
cores=cores,
)
else:
processor = SimpleProcessor(
cpu_type=cpu_enum,
isa=isa_enum,
num_cores=args.num_cores,
)
motherboard = SimpleBoard(
clk_freq="3GHz",
processor=processor,
memory=memory,
cache_hierarchy=cache_hierarchy,
)
# Set the workload
binary = Resource(args.resource, resource_directory=args.resource_directory)
motherboard.set_se_binary_workload(binary, arguments=args.arguments)
# Run the simulation
simulator = Simulator(board=motherboard)
simulator.run()
print(
"Exiting @ tick {} because {}.".format(
simulator.get_current_tick(), simulator.get_last_exit_event_cause()
)
)

1
tests/gem5/asmtest/tests.py
View File

@@ -180,6 +180,7 @@ for cpu_type in cpu_types:
config.base_dir,
"tests",
"gem5",
"asmtest",
"configs",
"simple_binary_run.py",
),

133
tests/gem5/configs/checkpoint.py
View File

@@ -1,133 +0,0 @@
# Copyright (c) 2015, 2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from multiprocessing import Process
import sys
import os
import m5
_exit_normal = ("target called exit()", "m5_exit instruction encountered")
_exit_limit = ("simulate() limit reached",)
_exitcode_done = 0
_exitcode_fail = 1
_exitcode_checkpoint = 42
def _run_step(name, restore=None, interval=0.5):
"""
Instantiate (optionally from a checkpoint if restore is set to the
checkpoitn name) the system and run for interval seconds of
simulated time. At the end of the simulation interval, create a
checkpoint and exit.
As this function is intended to run in its own process using the
multiprocessing framework, the exit is a true call to exit which
terminates the process. Exit codes are used to pass information to
the parent.
"""
if restore is not None:
m5.instantiate(restore)
else:
m5.instantiate()
e = m5.simulate(m5.ticks.fromSeconds(interval))
cause = e.getCause()
if cause in _exit_limit:
m5.checkpoint(name)
sys.exit(_exitcode_checkpoint)
elif cause in _exit_normal:
sys.exit(_exitcode_done)
else:
print(f"Test failed: Unknown exit cause: {cause}")
sys.exit(_exitcode_fail)
def run_test(root, interval=0.5, max_checkpoints=5):
"""
Run the simulated system for a fixed amount of time and take a
checkpoint, then restore from the same checkpoint and run until
the system calls m5 exit.
"""
cpt_name = os.path.join(m5.options.outdir, "test.cpt")
restore = None
checkpointed = False
for cpt_no in range(max_checkpoints):
# Create a checkpoint from a separate child process. This enables
# us to get back to a (mostly) pristine state and restart
# simulation from the checkpoint.
p = Process(
target=_run_step,
args=(cpt_name,),
kwargs={"restore": restore, "interval": interval},
)
p.start()
# Wait for the child to return
p.join()
# Restore from the checkpoint next iteration
restore = cpt_name
if p.exitcode == _exitcode_done:
if checkpointed:
print("Test done.", file=sys.stderr)
sys.exit(0)
else:
print(
"Test done, but no checkpoint was created.",
file=sys.stderr,
)
sys.exit(1)
elif p.exitcode == _exitcode_checkpoint:
checkpointed = True
else:
print("Test failed.", file=sys.stderr)
sys.exit(1)
# Maximum number of checkpoints reached. Just run full-speed from
# now on.
m5.instantiate()
e = m5.simulate()
cause = e.getCause()
if cause in _exit_normal:
sys.exit(0)
else:
print(f"Test failed: Unknown exit cause: {cause}")
sys.exit(1)

148
tests/gem5/configs/switcheroo.py
View File

@@ -1,148 +0,0 @@
# Copyright (c) 2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
import _m5
from m5.objects import *
m5.util.addToPath("../configs/")
from base_caches import *
class Sequential:
"""Sequential CPU switcher.
The sequential CPU switches between all CPUs in a system in
order. The CPUs in the system must have been prepared for
switching, which in practice means that only one CPU is switched
in. base_config.BaseFSSwitcheroo can be used to create such a
system.
"""
def __init__(self, cpus):
self.first_cpu = None
for (cpuno, cpu) in enumerate(cpus):
if not cpu.switched_out:
if self.first_cpu != None:
fatal("More than one CPU is switched in")
self.first_cpu = cpuno
if self.first_cpu == None:
fatal("The system contains no switched in CPUs")
self.cur_cpu = self.first_cpu
self.cpus = cpus
def next(self):
self.cur_cpu = (self.cur_cpu + 1) % len(self.cpus)
return self.cpus[self.cur_cpu]
def first(self):
return self.cpus[self.first_cpu]
def run_test(root, switcher=None, freq=1000, verbose=False):
"""Test runner for CPU switcheroo tests.
The switcheroo test runner is used to switch CPUs in a system that
has been prepared for CPU switching. Such systems should have
multiple CPUs when they are instantiated, but only one should be
switched in. Such configurations can be created using the
base_config.BaseFSSwitcheroo class.
A CPU switcher object is used to control switching. The default
switcher sequentially switches between all CPUs in a system,
starting with the CPU that is currently switched in.
Unlike most other test runners, this one automatically configures
the memory mode of the system based on the first CPU the switcher
reports.
Keyword Arguments:
switcher -- CPU switcher implementation. See Sequential for
an example implementation.
period -- Switching frequency in Hz.
verbose -- Enable output at each switch (suppressed by default).
"""
if switcher == None:
switcher = Sequential(root.system.cpu)
current_cpu = switcher.first()
system = root.system
system.mem_mode = type(current_cpu).memory_mode()
# Suppress "Entering event queue" messages since we get tons of them.
# Worse yet, they include the timestamp, which makes them highly
# variable and unsuitable for comparing as test outputs.
if not verbose:
_m5.core.setLogLevel(_m5.core.LogLevel.WARN)
# instantiate configuration
m5.instantiate()
# Determine the switching period, this has to be done after
# instantiating the system since the time base must be fixed.
period = m5.ticks.fromSeconds(1.0 / freq)
while True:
exit_event = m5.simulate(period)
exit_cause = exit_event.getCause()
if exit_cause == "simulate() limit reached":
next_cpu = switcher.next()
if verbose:
print("Switching CPUs...")
print(f"Next CPU: {type(next_cpu)}")
m5.drain()
if current_cpu != next_cpu:
m5.switchCpus(
system, [(current_cpu, next_cpu)], verbose=verbose
)
else:
print(
"Source CPU and destination CPU are the same,"
" skipping..."
)
current_cpu = next_cpu
elif (
exit_cause == "target called exit()"
or exit_cause == "m5_exit instruction encountered"
):
sys.exit(0)
else:
print(f"Test failed: Unknown exit cause: {exit_cause}")
sys.exit(1)

0
tests/gem5/configs/arm_generic.py → tests/gem5/fs/linux/arm/configs/arm_generic.py
View File

0
tests/gem5/configs/base_caches.py → tests/gem5/fs/linux/arm/configs/base_caches.py
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0
tests/gem5/configs/base_config.py → tests/gem5/fs/linux/arm/configs/base_config.py
View File

0
tests/gem5/configs/realview-minor-dual.py → tests/gem5/fs/linux/arm/configs/realview-minor-dual.py
View File

0
tests/gem5/configs/realview-minor.py → tests/gem5/fs/linux/arm/configs/realview-minor.py
View File

0
tests/gem5/configs/realview-o3-checker.py → tests/gem5/fs/linux/arm/configs/realview-o3-checker.py
View File

0
tests/gem5/configs/realview-o3-dual.py → tests/gem5/fs/linux/arm/configs/realview-o3-dual.py
View File

0
tests/gem5/configs/realview-o3.py → tests/gem5/fs/linux/arm/configs/realview-o3.py
View File

0
tests/gem5/configs/realview-simple-atomic-checkpoint.py → tests/gem5/fs/linux/arm/configs/realview-simple-atomic-checkpoint.py
View File

0
tests/gem5/configs/realview-simple-atomic-dual.py → tests/gem5/fs/linux/arm/configs/realview-simple-atomic-dual.py
View File

0
tests/gem5/configs/realview-simple-atomic.py → tests/gem5/fs/linux/arm/configs/realview-simple-atomic.py
View File

0
tests/gem5/configs/realview-simple-timing-dual-ruby.py → tests/gem5/fs/linux/arm/configs/realview-simple-timing-dual-ruby.py
View File

0
tests/gem5/configs/realview-simple-timing-dual.py → tests/gem5/fs/linux/arm/configs/realview-simple-timing-dual.py
View File

0
tests/gem5/configs/realview-simple-timing-ruby.py → tests/gem5/fs/linux/arm/configs/realview-simple-timing-ruby.py
View File

0
tests/gem5/configs/realview-simple-timing.py → tests/gem5/fs/linux/arm/configs/realview-simple-timing.py
View File

0
tests/gem5/configs/realview-switcheroo-atomic.py → tests/gem5/fs/linux/arm/configs/realview-switcheroo-atomic.py
View File

0
tests/gem5/configs/realview-switcheroo-full.py → tests/gem5/fs/linux/arm/configs/realview-switcheroo-full.py
View File

0
tests/gem5/configs/realview-switcheroo-noncaching-timing.py → tests/gem5/fs/linux/arm/configs/realview-switcheroo-noncaching-timing.py
View File

0
tests/gem5/configs/realview-switcheroo-o3.py → tests/gem5/fs/linux/arm/configs/realview-switcheroo-o3.py
View File

0
tests/gem5/configs/realview-switcheroo-timing.py → tests/gem5/fs/linux/arm/configs/realview-switcheroo-timing.py
View File

0
tests/gem5/configs/realview64-kvm-dual.py → tests/gem5/fs/linux/arm/configs/realview64-kvm-dual.py
View File

0
tests/gem5/configs/realview64-kvm.py → tests/gem5/fs/linux/arm/configs/realview64-kvm.py
View File

0
tests/gem5/configs/realview64-minor-dual.py → tests/gem5/fs/linux/arm/configs/realview64-minor-dual.py
View File

0
tests/gem5/configs/realview64-minor.py → tests/gem5/fs/linux/arm/configs/realview64-minor.py
View File

0
tests/gem5/configs/realview64-o3-checker.py → tests/gem5/fs/linux/arm/configs/realview64-o3-checker.py
View File

0
tests/gem5/configs/realview64-o3-dual-ruby.py → tests/gem5/fs/linux/arm/configs/realview64-o3-dual-ruby.py
View File

0
tests/gem5/configs/realview64-o3-dual.py → tests/gem5/fs/linux/arm/configs/realview64-o3-dual.py
View File

0
tests/gem5/configs/realview64-o3.py → tests/gem5/fs/linux/arm/configs/realview64-o3.py
View File

0
tests/gem5/configs/realview64-simple-atomic-checkpoint.py → tests/gem5/fs/linux/arm/configs/realview64-simple-atomic-checkpoint.py
View File

0
tests/gem5/configs/realview64-simple-atomic-dual.py → tests/gem5/fs/linux/arm/configs/realview64-simple-atomic-dual.py
View File

0
tests/gem5/configs/realview64-simple-atomic.py → tests/gem5/fs/linux/arm/configs/realview64-simple-atomic.py
View File

0
tests/gem5/configs/realview64-simple-timing-dual-ruby.py → tests/gem5/fs/linux/arm/configs/realview64-simple-timing-dual-ruby.py
View File

0
tests/gem5/configs/realview64-simple-timing-dual.py → tests/gem5/fs/linux/arm/configs/realview64-simple-timing-dual.py
View File

0
tests/gem5/configs/realview64-simple-timing-ruby.py → tests/gem5/fs/linux/arm/configs/realview64-simple-timing-ruby.py
View File

0
tests/gem5/configs/realview64-simple-timing.py → tests/gem5/fs/linux/arm/configs/realview64-simple-timing.py
View File

0
tests/gem5/configs/realview64-switcheroo-atomic.py → tests/gem5/fs/linux/arm/configs/realview64-switcheroo-atomic.py
View File

0
tests/gem5/configs/realview64-switcheroo-full.py → tests/gem5/fs/linux/arm/configs/realview64-switcheroo-full.py
View File

0
tests/gem5/configs/realview64-switcheroo-o3.py → tests/gem5/fs/linux/arm/configs/realview64-switcheroo-o3.py
View File

0
tests/gem5/configs/realview64-switcheroo-timing.py → tests/gem5/fs/linux/arm/configs/realview64-switcheroo-timing.py
View File

2
tests/gem5/fs/linux/arm/run.py
View File

@@ -62,7 +62,7 @@ gem5_root = sys.argv[3]
# path setup
sys.path.append(joinpath(gem5_root, "configs"))
tests_root = joinpath(gem5_root, "tests")
sys.path.append(joinpath(tests_root, "gem5", "configs"))
sys.path.append(joinpath(tests_root, "gem5", "fs", "linux", "arm", "configs"))
exec(compile(open(config).read(), config, "exec"))

33
tests/gem5/fs/linux/arm/test.py
View File

@@ -129,7 +129,16 @@ for name in arm_fs_quick_tests:
valid_hosts = constants.supported_hosts
args = [
joinpath(config.base_dir, "tests", "gem5", "configs", name + ".py"),
joinpath(
config.base_dir,
"tests",
"gem5",
"fs",
"linux",
"arm",
"configs",
name + ".py",
),
path,
config.base_dir,
]
@@ -147,7 +156,16 @@ for name in arm_fs_quick_tests:
for name in arm_fs_long_tests:
args = [
joinpath(config.base_dir, "tests", "gem5", "configs", name + ".py"),
joinpath(
config.base_dir,
"tests",
"gem5",
"fs",
"linux",
"arm",
"configs",
name + ".py",
),
path,
config.base_dir,
]
@@ -164,7 +182,16 @@ for name in arm_fs_long_tests:
for name in arm_fs_long_tests_arm_target:
args = [
joinpath(config.base_dir, "tests", "gem5", "configs", name + ".py"),
joinpath(
config.base_dir,
"tests",
"gem5",
"fs",
"linux",
"arm",
"configs",
name + ".py",
),
path,
config.base_dir,
]

0
tests/gem5/configs/download_check.py → tests/gem5/gem5_resources/configs/download_check.py
View File

7
tests/gem5/gem5_resources/test_download_resources.py
View File

@@ -38,7 +38,12 @@ gem5_verify_config(
fixtures=(),
verifiers=(),
config=joinpath(
config.base_dir, "tests", "gem5", "configs", "download_check.py"
config.base_dir,
"tests",
"gem5",
"gem5_resources",
"configs",
"download_check.py",
),
config_args=["--download-directory", resource_path],
valid_isas=(constants.all_compiled_tag,),

130
tests/gem5/insttest_se/configs/simple_binary_run.py Normal file
View File

@@ -0,0 +1,130 @@
# Copyright (c) 2021 The Regents of the University of California
# Copyright (c) 2022 Google Inc
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
"""
A run script for a very simple Syscall-Execution running simple binaries.
The system has no cache heirarchy and is as "bare-bones" as you can get in
gem5 while still being functinal.
"""
from gem5.resources.resource import Resource
from gem5.components.processors.cpu_types import (
get_cpu_types_str_set,
get_cpu_type_from_str,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.boards.mem_mode import MemMode
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
from gem5.isas import get_isa_from_str, get_isas_str_set, ISA
from m5.util import fatal
import argparse
import importlib
cpu_types_string_map = {
CPUTypes.ATOMIC: "AtomicSimpleCPU",
CPUTypes.O3: "O3CPU",
CPUTypes.TIMING: "TimingSimpleCPU",
CPUTypes.KVM: "KvmCPU",
CPUTypes.MINOR: "MinorCPU",
}
parser = argparse.ArgumentParser(
description="A gem5 script for running simple binaries in SE mode."
)
parser.add_argument(
"resource", type=str, help="The gem5 resource binary to run."
)
parser.add_argument(
"cpu", type=str, choices=get_cpu_types_str_set(), help="The CPU type used."
)
parser.add_argument(
"isa", type=str, choices=get_isas_str_set(), help="The ISA used"
)
parser.add_argument(
"--resource-directory",
type=str,
required=False,
help="The directory in which resources will be downloaded or exist.",
)
parser.add_argument(
"--arguments",
type=str,
action="append",
default=[],
required=False,
help="The input arguments for the binary.",
)
args = parser.parse_args()
# Setup the system.
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600()
isa_enum = get_isa_from_str(args.isa)
cpu_enum = get_cpu_type_from_str(args.cpu)
processor = SimpleProcessor(
cpu_type=cpu_enum,
isa=isa_enum,
num_cores=1,
)
motherboard = SimpleBoard(
clk_freq="3GHz",
processor=processor,
memory=memory,
cache_hierarchy=cache_hierarchy,
)
# Set the workload
binary = Resource(args.resource, resource_directory=args.resource_directory)
motherboard.set_se_binary_workload(binary, arguments=args.arguments)
# Run the simulation
simulator = Simulator(board=motherboard)
simulator.run()
print(
"Exiting @ tick {} because {}.".format(
simulator.get_current_tick(), simulator.get_last_exit_event_cause()
)
)

1
tests/gem5/insttest_se/test.py
View File

@@ -52,6 +52,7 @@ for isa in test_progs:
config.base_dir,
"tests",
"gem5",
"insttest_se",
"configs",
"simple_binary_run.py",
),

0
tests/gem5/configs/boot_kvm_fork_run.py → tests/gem5/kvm_fork_tests/configs/boot_kvm_fork_run.py
View File

7
tests/gem5/kvm_fork_tests/test_kvm_fork_run.py
View File

@@ -64,7 +64,12 @@ def test_kvm_fork_run(cpu: str, num_cpus: int, mem_system: str, length: str):
verifiers=verifiers,
fixtures=(),
config=joinpath(
config.base_dir, "tests", "gem5", "configs", "boot_kvm_fork_run.py"
config.base_dir,
"tests",
"gem5",
"kvm_fork_tests",
"configs",
"boot_kvm_fork_run.py",
),
config_args=[
"--cpu",

0
tests/gem5/configs/boot_kvm_switch_exit.py → tests/gem5/kvm_switch_tests/configs/boot_kvm_switch_exit.py
View File

1
tests/gem5/kvm_switch_tests/test_kvm_cpu_switch.py
View File

@@ -67,6 +67,7 @@ def test_kvm_switch(cpu: str, num_cpus: int, mem_system: str, length: str):
config.base_dir,
"tests",
"gem5",
"kvm_switch_tests",
"configs",
"boot_kvm_switch_exit.py",
),

103
tests/gem5/m5_util/configs/simple_binary_run.py Normal file
View File

@@ -0,0 +1,103 @@
# Copyright (c) 2021 The Regents of the University of California
# Copyright (c) 2022 Google Inc
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
"""
A run script for a very simple Syscall-Execution running simple binaries.
The system has no cache heirarchy and is as "bare-bones" as you can get in
gem5 while still being functinal.
"""
from gem5.resources.resource import Resource
from gem5.components.processors.cpu_types import (
get_cpu_types_str_set,
get_cpu_type_from_str,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.boards.mem_mode import MemMode
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
from gem5.isas import get_isa_from_str, get_isas_str_set, ISA
from m5.util import fatal
import argparse
import importlib
parser = argparse.ArgumentParser(
description="A gem5 script for running simple binaries in SE mode."
)
parser.add_argument(
"resource", type=str, help="The gem5 resource binary to run."
)
parser.add_argument(
"--resource-directory",
type=str,
required=False,
help="The directory in which resources will be downloaded or exist.",
)
args = parser.parse_args()
# Setup the system.
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600()
processor = SimpleProcessor(
cpu_type=CPUTypes.ATOMIC,
isa=ISA.X86,
num_cores=1,
)
motherboard = SimpleBoard(
clk_freq="3GHz",
processor=processor,
memory=memory,
cache_hierarchy=cache_hierarchy,
)
# Set the workload
binary = Resource(args.resource, resource_directory=args.resource_directory)
motherboard.set_se_binary_workload(binary)
# Run the simulation
simulator = Simulator(board=motherboard)
simulator.run()
print(
"Exiting @ tick {} because {}.".format(
simulator.get_current_tick(), simulator.get_last_exit_event_cause()
)
)

9
tests/gem5/m5_util/test_exit.py
View File

@@ -57,14 +57,17 @@ gem5_verify_config(
verifiers=[a],
fixtures=(),
config=joinpath(
config.base_dir, "tests", "gem5", "configs", "simple_binary_run.py"
config.base_dir,
"tests",
"gem5",
"m5_util",
"configs",
"simple_binary_run.py",
),
config_args=[
"x86-m5-exit",
"atomic",
"--resource-directory",
resource_path,
"x86",
],
valid_isas=(constants.all_compiled_tag,),
)

0
tests/gem5/configs/runtime_isa_check.py → tests/gem5/multi_isa/configs/runtime_isa_check.py
View File

0
tests/gem5/configs/supported_isa_check.py → tests/gem5/multi_isa/configs/supported_isa_check.py
View File

3
tests/gem5/multi_isa/test_multi_isa.py
View File

@@ -49,6 +49,7 @@ for isa in isa_map.keys():
config.base_dir,
"tests",
"gem5",
"multi_isa",
"configs",
"runtime_isa_check.py",
),
@@ -66,6 +67,7 @@ for isa in isa_map.keys():
config.base_dir,
"tests",
"gem5",
"multi_isa",
"configs",
"supported_isa_check.py",
),
@@ -86,6 +88,7 @@ for isa in isa_map.keys():
config.base_dir,
"tests",
"gem5",
"multi_isa",
"configs",
"supported_isa_check.py",
),

0
tests/gem5/configs/parsec_disk_run.py → tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py
View File

7
tests/gem5/parsec_benchmarks/test_parsec.py
View File

@@ -57,7 +57,12 @@ def test_parsec(
verifiers=(),
fixtures=(),
config=joinpath(
config.base_dir, "tests", "gem5", "configs", "parsec_disk_run.py"
config.base_dir,
"tests",
"gem5",
"parsec_benchmarks",
"configs",
"parsec_disk_run.py",
),
config_args=[
"--cpu",

94
tests/gem5/replacement_policies/configs/run_replacement_policy.py Normal file
View File

@@ -0,0 +1,94 @@
# Copyright (c) 2022 The Regents of the University of California
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import argparse
from importlib.machinery import SourceFileLoader
from cache_hierarchies import ModMIExampleCacheHierarchy
import m5
from m5.debug import flags
from m5.objects import Root
from gem5.components.boards.test_board import TestBoard
from gem5.components.memory.simple import SingleChannelSimpleMemory
from gem5.components.processors.complex_generator import ComplexGenerator
argparser = argparse.ArgumentParser()
argparser.add_argument(
"config_name",
type=str,
help="Name of the python file "
"including the defintion of a python generator and "
"importing the right replacement policy. The python "
"generator should only assume one positional argument "
"and be named python_generator. The replacement policy"
" should be imported as rp.",
)
argparser.add_argument(
"config_path",
type=str,
help="Path to the python file" "specified by config_name.",
)
args = argparser.parse_args()
module = SourceFileLoader(args.config_name, args.config_path).load_module()
python_generator = module.python_generator
rp_class = module.rp
flags["RubyHitMiss"].enable()
cache_hierarchy = ModMIExampleCacheHierarchy(rp_class)
memory = SingleChannelSimpleMemory(
latency="30ns",
latency_var="0ns",
bandwidth="12.8GiB/s",
size="512MiB",
)
generator = ComplexGenerator()
generator.set_traffic_from_python_generator(python_generator)
# We use the Test Board. This is a special board to run traffic generation
# tasks
motherboard = TestBoard(
clk_freq="1GHz",
generator=generator, # We pass the traffic generator as the processor.
memory=memory,
cache_hierarchy=cache_hierarchy,
)
root = Root(full_system=False, system=motherboard)
motherboard._pre_instantiate()
m5.instantiate()
generator.start_traffic()
print("Beginning simulation!")
exit_event = m5.simulate()
print(f"Exiting @ tick {m5.curTick()} because {exit_event.getCause()}.")

3
tests/gem5/replacement_policies/test_replacement_policies.py
View File

@@ -44,7 +44,8 @@ def test_replacement_policy(config_name: str, config_path: str) -> None:
config.base_dir,
"tests",
"gem5",
"replacement-policies",
"replacement_policies",
"configs",
"run_replacement_policy.py",
),
config_args=[config_name, config_path],

0
tests/gem5/configs/riscv_boot_exit_run.py → tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py
View File

1
tests/gem5/riscv_boot_tests/test_linux_boot.py
View File

@@ -80,6 +80,7 @@ def test_boot(
config.base_dir,
"tests",
"gem5",
"riscv_boot_tests",
"configs",
"riscv_boot_exit_run.py",
),

49
tests/gem5/configs/simple_binary_run.py → tests/gem5/se_mode/hello_se/configs/simple_binary_run.py
View File

@@ -1,4 +1,5 @@
# Copyright (c) 2021 The Regents of the University of California
# Copyright (c) 2022 Google Inc
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -45,9 +46,20 @@ from gem5.components.processors.simple_core import SimpleCore
from gem5.components.boards.mem_mode import MemMode
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
from gem5.isas import get_isa_from_str, get_isas_str_set
from gem5.isas import get_isa_from_str, get_isas_str_set, ISA
from m5.util import fatal
import argparse
import importlib
cpu_types_string_map = {
CPUTypes.ATOMIC: "AtomicSimpleCPU",
CPUTypes.O3: "O3CPU",
CPUTypes.TIMING: "TimingSimpleCPU",
CPUTypes.KVM: "KvmCPU",
CPUTypes.MINOR: "MinorCPU",
}
parser = argparse.ArgumentParser(
description="A gem5 script for running simple binaries in SE mode."
@@ -65,13 +77,6 @@ parser.add_argument(
"isa", type=str, choices=get_isas_str_set(), help="The ISA used"
)
parser.add_argument(
"-b",
"--base-cpu-processor",
action="store_true",
help="Use the BaseCPUProcessor instead of the SimpleProcessor.",
)
parser.add_argument(
"-r",
"--resource-directory",
@@ -104,28 +109,14 @@ args = parser.parse_args()
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600()
if args.base_cpu_processor:
cores = [
BaseCPUCore(
core=SimpleCore.cpu_simobject_factory(
cpu_type=get_cpu_type_from_str(args.cpu),
isa=get_isa_from_str(args.isa),
core_id=i,
),
isa=get_isa_from_str(args.isa),
)
for i in range(args.num_cores)
]
isa_enum = get_isa_from_str(args.isa)
cpu_enum = get_cpu_type_from_str(args.cpu)
processor = BaseCPUProcessor(
cores=cores,
)
else:
processor = SimpleProcessor(
cpu_type=get_cpu_type_from_str(args.cpu),
isa=get_isa_from_str(args.isa),
num_cores=args.num_cores,
)
processor = SimpleProcessor(
cpu_type=cpu_enum,
isa=isa_enum,
num_cores=args.num_cores,
)
motherboard = SimpleBoard(
clk_freq="3GHz",

8
tests/gem5/se_mode/hello_se/test_hello_se.py
View File

@@ -96,7 +96,13 @@ def verify_config(isa, binary, cpu, hosts, verifier, input):
fixtures=(),
verifiers=(verifier,),
config=joinpath(
config.base_dir, "tests", "gem5", "configs", "simple_binary_run.py"
config.base_dir,
"tests",
"gem5",
"se_mode",
"hello_se",
"configs",
"simple_binary_run.py",
),
config_args=[
binary,

8
tests/gem5/se_mode/hello_se/test_se_multicore.py
View File

@@ -40,7 +40,13 @@ gem5_verify_config(
fixtures=(),
verifiers=(),
config=joinpath(
config.base_dir, "tests", "gem5", "configs", "simple_binary_run.py"
config.base_dir,
"tests",
"gem5",
"se_mode",
"hello_se",
"configs",
"simple_binary_run.py",
),
config_args=[
"x86-hello64-static",

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