Commit Graph

13716 Commits

Author SHA1 Message Date
Jarvis Jia
a68e842332 mem-ruby: Fix replacement policy in MESI_Two_Level
The current MESI_Two_Level protocol's L1 caches updates the MRU information twice per request on misses -- once when the request reaches Ruby and once when the miss is returned from another level of the memory hierarchy.

Although this approach does not cause any correctness bugs for replacement policies like LRU since this request is the LRU in both cases, it does not work correctly for other policies like SecondChance and LFU, where updating the information twice (for misses) causes them to devolve to LRU.

Note that this was not directly a problem with Ruby previously, because it only supported LRU-based policies that were unaffected by this.  However, with the integration of 20879 Ruby now uses the same replacement policies as Classic (which has additional, non-LRU based replacement policies).

This patch resolves this problem by not updating the MRU information a second time for the misses. It has been tested and validated with the replacement policy tests.

Change-Id: I9e7e96a9d6c09f3d6b7daae7115ef091ac3bdc08
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64371
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2022-10-20 01:03:39 +00:00
Jason Lowe-Power
b3372a7053 stdlib: Update TestBoard to work with Simulator
This change makes minor updates to the TestBoard so that it can work
nicely with the Simulator module.

This change also makes the cache hierarchy optional for the TestBoard.

Change-Id: If46d53779164e87b6fc06176355be6b4ae05aa99
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64017
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Mahyar Samani <msamani@ucdavis.edu>
2022-10-18 21:40:59 +00:00
Jason Lowe-Power
b8e6e3aa43 python: Update -c to work like normal python
In python, when you use -c it consumes all subsequent parameters and
appends them to argv. Now, gem5 and python behave the same with -c.

Python:
> python -c "import sys; print(sys.argv)" --hello -j
['-c', '--hello', '-j']

gem5:
> gem5.opt -c "import sys; print(sys.argv)" --hello -j
gem5 Simulator System.  https://www.gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 version [DEVELOP-FOR-22.1]
gem5 compiled Oct 17 2022 15:47:46
gem5 started Oct 17 2022 15:53:45
gem5 executing on challenger, pid 4021103
command line: build/ALL/gem5.opt -c 'import sys; print(sys.argv)' --hello -j

['-c', '--hello', '-j']

Change-Id: I53e87712be9523e0583149235c9787c92618f884
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63151
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2022-10-18 18:00:02 +00:00
Yu-hsin Wang
32e7ce3f19 fastmodel: improve debug message for resource not found
The conversion logic between gem5 register id and iris resouce id is
duplicated in read and write function. Some of them also doesn't handle
the invalid id correctly. This change wraps the logic, fixes them, and
improves the debug messages by printing the register names.

Change-Id: I093d05f5f06d804d5f01988c2a7ffa60244c5516
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64651
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
2022-10-18 12:11:25 +00:00
Yu-hsin Wang
ca31ce92a1 scons: fix systrace header test
Latest compilers default checks the unused and uninitialized. Those
checks result in false negative of the header test. We fix it by
replacing the temp variable to (void *)1.

Btw, (void *)0 not works here because the function is declare with nonnull.
https://elixir.bootlin.com/glibc/latest/source/debug/execinfo.h#L38

Change-Id: I3b51faf7595b861bfbd131c0a42fd6d78a5e9698
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64652
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2022-10-18 12:11:25 +00:00
Jason Yu
bc914c949f sim,sim-se: Fixes the bug of missing "/" in path resolution
The syscall emulation did not correctly handle the scenario where the
base path does not end with "/". The "/" should be appended first
before the file name is appended. This commit fixes this bug.

Change-Id: I9a9b38d1885e46b2a0e42018fd7d68010c70133c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64471
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-18 05:49:24 +00:00
Giacomo Travaglini
221dc014db arch-arm: Use scoped enum for ExceptionClass
Change-Id: I42ce3c31dfe89b75658db4a79c6a29a43fd0d82b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64411
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
2022-10-17 09:00:59 +00:00
Giacomo Travaglini
a4dcd58569 arch-arm: Fix QDADD/QDSUB implementation
This got broken by a recent commit [1] which converted a bitwise
OR into the boolean version. While it conceptually made sense
as the saturateOp returns a boolean value, it is not taking
into consideration that saturateOp modifies the first argument
and the boolean version short-circuits the expression preventing
the second expression from being run if the first one is true

Therefore providing an incorrect midRes value.

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/64172

Change-Id: Ibb9b3d37dcccda006006650ef759cdfe385dcfe2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64612
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
2022-10-17 09:00:16 +00:00
Yu-hsin Wang
21020aa778 systemc: prevent from invalidate callback re-registration
Remove the redundant callback to save the memory.

Change-Id: Iafa6ada06f62ac2928a580c25ebbcbbe3f195670
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64474
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
2022-10-17 02:04:40 +00:00
Adrián Herrera Arcila
9e76e7a321 scons: fix protobuf action for imports
The current protoc_action generates declarations that impose the requirement
for .proto files to import from the BUILDDIR. This prevents .proto files to
import themselves relative to their own directory.

For example, if there are two files build/pkg/a.proto and build/pkg/b.proto,
and b.proto imports a.proto, it must do so as "import pkg/a.proto", as opposed
to "import a.proto"; otherwise, the generated declaration will give rise to a
compilation error.

This is a problem for EXTRAS where .proto files are gem5-independent, so
they cannot import from gem5's build directory. An example is
https://github.com/ARM-software/ATP-Engine

This commit changes the protoc_action so that declarations are generated
relative to the SOURCE directory. This enables .proto files to import
other .proto files within the same directory.

Note it is not possible to import other .proto files in different
directories, but support for it is not currently necessary.

More details on the proto path:
https://developers.google.com/protocol-buffers/docs/reference/cpp-generated#invocation

Related:
https://gem5-review.googlesource.com/c/public/gem5/+/55903

Change-Id: Ib3e67ae817f8ad0b6803c90d23469267eff16178
Signed-off-by: Adrián Herrera Arcila <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64491
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
2022-10-15 14:22:03 +00:00
Giacomo Travaglini
039e9438c1 arch-arm: Fix linking error in aapcs64 unittests
This is fixing the undefined reference exposed by our nightly
run [1] by including the arch/arm/regs/int.cc source (needed
for the IntRegClassOps::flatten implementation) plus
sim/cur_tick.cc

[1]: https://www.mail-archive.com/gem5-dev@gem5.org/msg43249.html

Change-Id: I51a616ca2ef513f0068e531ebee17172d68cc738
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64611
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-15 13:24:39 +00:00
Jason Yu
e501078787 sim-se,arch-riscv: Fixes file-related flags for riscv64 target
Previous file-related flags for the riscv64-unknown-linux-gnu target
do not match the actual
values, leading to incorrect behaviours in certain emulated syscalls.
This commit fixes the problem.

Change-Id: I38ff624c00e46e37672510af5a10f527b5f0842a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64472
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-10-14 17:18:06 +00:00
Matthew Poremba
a648be2338 dev-amdgpu: Add an SDMA data debug flag
This debug flag is used to print spammy SDMA DPRINTFs, such as an SDMA
copy printing the data of large transfers 8 bytes per line at a time. For
those prints, the SDMAEngine flag will now only print the first and last
qword of the transfer and the new SDMAData flag is needed for verbose
data printing. This makes the SDMAEngine flag still useful for verifying
copies in applications with predictable data such as square.

Additionally, the memory allocation/deallocation done solely for a print
statement is removed in favor of casting the data to the printed type.

Change-Id: I18c1918ef9085cca4570f79881ee63d510ccc32f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64452
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2022-10-13 20:17:00 +00:00
Matthew Poremba
e48285c244 arch-vega: Implement PDE2 and PDE1 as PTE
Page directory entries (PDEs) can be interpreted as leaf node page
table entries (PTEs) if the "p" bit is set. This is used for flexible
page sizes in Vega. Currently there is only support for PDE level 0
entries which can be interpreted as 2MB pages. This changeset adds
support for PDE1 and PDE2 which can be used to represent 1GB and 512GB
pages. PDE1-as-PTE entries can be tested and were verified on
applications by allocating >2GB of data. PDE0 is untested due to being
too large for simulation, but the implementation is similar to PDE0
and PDE1.

Change-Id: I801cbb5ec79110d57d2db760cc689c2e5778f9bb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64451
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2022-10-13 20:17:00 +00:00
Yu-hsin Wang
a713d333e0 sysetmc: add missing NO_ACCESS flags in get_direct_mem_ptr
In the previous refactor, I remove the NO_ACCESS flag by incident. This
change adds the flag back.

Previous refactor: https://gem5-review.googlesource.com/c/public/gem5/+/63771

Change-Id: Ifd49b11ef6f76903f022072dd81020dea50fa103
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64392
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
2022-10-12 16:41:31 +00:00
Yu-hsin Wang
958b7f8ee8 sysetmc: fix the leak in TlmToGem5Bridge
In the previous refactor, I made a mistake causing memory leak. This
change fix the mistake.

Previous refactor: https://gem5-review.googlesource.com/c/public/gem5/+/63771

Change-Id: I244a990e00507a6b065af38c61f061bc5d72d90e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64391
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-12 16:41:31 +00:00
Zhantong Qiu
9ac075ea36 stdlib: added errout and output file option in SE process
In the set_se_binary_workload(), added stdout_file and stderr_file
arguments to setup process.errout and process.output.

Change-Id: I54db2248578f485a633d6b6212fa6c62bcbca4de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64151
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-11 00:32:50 +00:00
Bobby R. Bruce
6e182b025d mem-ruby: Fix clang-14 compilation warning "use of bitwise"
Clang Version 14 throws a warning "use of bitwise '&/|' with boolean
operands" for cases where bitwise operations are used where boolean
operations are intended.

This occurred in "WriteMast.hh", "data.isa", and "decode.cc" where
boolean values were being compared using the bitwise operands. While
bitwise operations are equivalent, they have been changed to boolean
operations in this patch to avoid the clang-14 warning.

Change-Id: Ic7583e13a325661712c75c8e1b234c4878832352
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64172
Reviewed-by: Tom Rollet <tom.rollet@huawei.com>
Reviewed-by: Kunal Pai <kunpai@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-10 17:24:03 +00:00
Bobby R. Bruce
abad2d6532 mem: Fix 'unused variable' warnings
The `Addr line_addr` in "src/mem/snoop_filter.cc" variable was only
used in an assert, stripped when compiling gem5.fast.
Clang-13 throws a warning for this variable. This has been fixed by
merging the variable and associated logic into the assert statement.

The variables in inet.cc and Sequencer.cc were also causing an 'unused
variable' warning to be thrown due to variables that were only used in
assert statements. In these cases the logic could not be moved into the
assert statement and, as such, the `GEM5_VAR_USED` MACRO is used to
remove this warning.

Change-Id: I6511d0863608c38b79e4558c7dcf35a323fe8362
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64171
Reviewed-by: Kunal Pai <kunpai@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-10 17:24:03 +00:00
Jason Lowe-Power
d2a6d2f7ee stdlib: Add _post_instantiate function
This function will be called on the board after m5.instantiate is
called. This is useful, for instance, to start traffic generators.
Currently all implementations simply `pass`.

Change-Id: Ie2ab3fdddca5f3978d98191e5c08504561587fbb
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64016
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-07 23:52:14 +00:00
Jason Lowe-Power
55f80ae0a1 stdlib: Allow cache_hierarchy to be optional
This changeset makes the cache_hierarchy optional on the board. This
will allow us to enable the TestBoard to have memory directly connected
to the traffic generator.

Change-Id: I62d310e74c43724ea38e3b71a4d91d9e06d6e855
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64015
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-07 23:51:18 +00:00
Jason Lowe-Power
007a99e9a0 stdlib: Update the default exit events and warning
This change updates the default actions taken when the user doesn't
specify generators for the exit events in the simulator. Rather than
defining default generators, this change makes the generators more
generic and gives a new decorator to mark them as default.

This change then updates the default generators in the simulator and
only makes some of them issue a default warning. For exit events such as
EXIT, the default will no longer print a warning.

Change-Id: I5552f52392f3aea577034ed278a9ff9e8b5b0b01
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64251
Reviewed-by: Zhantong Qiu <ztqiu@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-07 23:50:41 +00:00
Yu-hsin Wang
0e20edac34 systemc: fix flexible conversion when reusing transactions
To make the all extension states correct, we still need to proceed the
plugins when reusing the transactions, since we don't know the detail of
the plugins.

Change-Id: I18acd64f54be4c82a0678b98e834ea9548de1f58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63871
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-07 09:40:43 +00:00
Matthew Poremba
ec696c00b2 gpu-compute: Add missing initial reg state in WF
There are two initial scalar register fields that are not initialized in
the wavefront when a task is dispatch. This changeset adds the missing
DispatchId and PrivateSegSize fields. These fields are typically used
when an application is compiled with debug support and are typically not
used in the applications in gem5's test suite.

Change-Id: I5b5fa75e4badfd9ba7588e4cd485ebf75fd5d627
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64191
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 23:14:40 +00:00
Matthew Poremba
925b1b5c8e arch-vega: Implement V_XAD_U32 instruction
Used in rodinia:heartwall.  This instruction is new in vega and does not
exist in GCN3.

Change-Id: I6127290d1c85688a7f82e149e97762ca55e05fc6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63972
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 16:42:40 +00:00
Quentin Forcioli
e94c9f362c base: singleStep can't be interupted by trap from other thread.
Change-Id: I0c46e3ea623b304b7ae8f8867d90c5d0008e8b3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63533
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:35:40 +00:00
Quentin Forcioli
bff69e4792 base: adding a scheduleTrapEvent
This function centralize setting up a new trapEvent making sure that
the contextId match with the ThreadContext use for the Event.

Change-Id: I2a5f77da049d140b9ceffd42011fd8a1da59092e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63532
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-06 14:35:23 +00:00
Quentin Forcioli
2ae9692dfe base, sim: Adding support for message to GDB from python
Adding a small python function that allows to display
messages directly in GDB from the python interpreter.
This function is inside the Workload SimObject
(The stub is not a SimObject).
ex:
     system.workload.sendToGdb("message to display")

Change-Id: I46ddae079b10d298743e023f95bf15608f50e358
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63531
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:34:55 +00:00
Quentin Forcioli
eeaeee15aa base: adding queryAttached and querySymbol to GDB
In some cases/version these queries might be needed
to make the remote GDB connect correctly to the stub.

Change-Id: I98cdc9b4a952b4dc64f9357e6148af6e3351ef92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63530
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:34:30 +00:00
Quentin Forcioli
3e43603dcc base: adding support for O packet
O packet allow the GDB stub to send a message to display for the GDB
remote.
This function could be used to implement certains specific command
response.

Change-Id: I1c9a1ca956efcf19c93a8503d97c1fb27f555966
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63529
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:34:15 +00:00
Quentin Forcioli
bb78d14c08 base: Adding stop reason and T Packet to the GDB stub
The remote protocol describes 2 type of stop respond packet.

S packets (which are the one that where used before) and T packets.

T packet support multiple fields to give more information about:
   - thread/core which stopped
   - registers values
   - A stopReason string that are predefined value and that can
     differentiate between different types of break that would
     issue the same signal.

Change-Id: Id8ed7115898bf825dd14395f586c393d6f5aa2bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63528
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:33:40 +00:00
Quentin Forcioli
cee2aa39b6 base: cmdIsThreadAlive implementation
Some GDB implementations, specifically ARM's, needed this to be able to
switch between thread.

Change-Id: I0d4db0c008c336eac51008bcfefd04c375c333f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63527
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:33:23 +00:00
Quentin Forcioli
e6287f7b19 base: making GDB's getbyte and send more resilient
Add a try_getbyte function that feature a timeout. This function uses
select to detect update on the file descriptor used to communicate with
the remote.
It is used to implement getbyte and to clean the file
descriptor before sending a message with send.

Now getbyte and send can recover from certains error like interruption
by other signals (EINTR) or delays causing the remote server to send
error packet to the stub.

Change-Id: Ie06845ba59dee0ad831632d5bc2b15132c9d5450
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63526
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-06 14:32:29 +00:00
Quentin Forcioli
832b0ee6b9 base: Adding multi-letter command support to GDB stub
The GDB remote protocol defines multi-letter
 command names that start with a "v".
I added vKill and vMustReplyEmpty as an example.

Change-Id: I10177729c7d6a3e7d469ce66a63bfcfd21aa6f83
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63525
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2022-10-06 14:32:19 +00:00
Ayaz Akram
335d2e187e arch-x86, mem: Add support to tag tlb entries with PCID
This change adds support to tag tlb entries with PCID to
avoid the conflict between different processes with same
virtual addresses sharing a tlb. This eventually is required
to enable smt support for x86.

Change-Id: Ia91dc371482793962e3fc83afe7a3fd2cdb60eab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35836
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-05 17:44:59 +00:00
Ayaz Akram
09aeb51350 arch-x86, mem: Add support for PCID to x86
This change adds Process Context Identifier (PCID) support
to x86, so that tlb entries can be tagged using pcid.

Change-Id: I695eccc4b08476b32d4b3728fc3c42b2ad6f5a28
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35835
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-05 17:44:59 +00:00
Ayaz Akram
ea26611a01 arch-x86: Assign thread context id to APIC id
This change tries to enable a unique APIC id for a single thread
to enable smt support for x86

Change-Id: I3e7034b358623577c5ad4be3e51f08e48291ce49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35837
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-05 17:44:59 +00:00
Giacomo Travaglini
597a2ce4c1 arch-arm: Add ArmRelease factory function to be used in KVM mode
From gem5 v22.0, EL2 and EL3 are automatically implemented
in the default release object [1]. This means any FS simulation
will start at EL3, which is the highest implemented EL.

Unfortunately this doesn't work in KVM mode, which is assuming
a VM does not start at EL3:

As soon as updateKvmState is called [2] gem5 tries to set
the VM PSTATE to EL3 and KVM fails the ioctl PSTATE write

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/51011
[2]: https://github.com/gem5/gem5/blob/v22.0.0.2/\
    src/arch/arm/kvm/armv8_cpu.cc#L237

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Icf951bcfb47e0c2ff9abe64b1b9006934303ad48
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64072
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-04 09:45:20 +00:00
Earl Ou
317bfd62bd dev: fix device number check error in IDE controller
Fixed a typo between 3 and 4.

Change-Id: I1470e30c4d472587db0b9da5512b24ab92f1fd65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64052
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2022-10-04 01:21:37 +00:00
Giacomo Travaglini
4f09acb2f5 arch-arm: Add the remove method to the ArmRelease class
This allows to remove an extension from a release object

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I60189c37ffcefab991955c3d0bb560a6a79f0977
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64071
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-03 23:00:57 +00:00
Giacomo Travaglini
7c0ab07ee2 dev-arm: Fix GICv3 GICD_ITARGETSR address range
According to the GICv3 manual, GICD_ITARGETSR address range goes from
0x0800 to 0x0c00 (as already implemented in the GICv2 model [1])

[1]: https://github.com/gem5/gem5/blob/v22.0.0.0/\
    src/dev/arm/gic_v2.cc#L64

Change-Id: I064e91d070d1a7b79f41a06ffd2197e4c07dae32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64074
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-03 17:45:10 +00:00
Giacomo Travaglini
336e732d54 misc: Replace namespace Trace with lowercase trace
This is what the coding style demands

Change-Id: Ida6a71ad9c2c02cccd584bbaf37a6da751c5b856
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63891
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
2022-10-02 16:30:15 +00:00
Matthew Poremba
2f1d67f8fe dev-amdgpu: Remove cached copy of device memory
This map was originally used for fast access to the GART table. It is no
longer needed as the table has been moved to the AMDGPUVM class. Along
with commit 12ec5f9172 which reads
functionally from device memory, this table is no longer needed and is
essentially a duplicate copy of device memory for anything written over
the PCI BAR.

This changeset removes the map entirely which will reduce the memory
footprint of simulations and potentially avoid stale copies of data
when reading over the PCI BAR.

Change-Id: I312ae38f869c6a65e50577b1c33dd055078aaf32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63951
Reviewed-by: Matt Sinclair <mattdsinclair.wisc@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2022-10-01 14:04:45 +00:00
paikunal
4662e18981 stdlib: Edit RiscvMatched RTC
Fixed the bug that made FS mode break.
Changed RTC value as fix.

Change-Id: I0effa1ecd32a8a8845e619d940f8e0efe549cfc1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64013
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-10-01 03:44:06 +00:00
Carlos Falquez
a57f08f355 mem-garnet: Add masked functionalRead support
Recently the CHI protocol was introduced in Ruby.
The protocol introduces an alternative interface for
functional reads:

bool functionalRead(PacketPtr, WriteMask&)

This commit adds functionalRead(PacketPtr, WriteMask&)
implementations for various Garnet components.

Change-Id: Idd571899d679407b7b000c1a83a0a5420868cf28
Signed-off-by: Carlos Falquez <c.falquez@fz-juelich.de>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46900
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-09-29 06:46:21 +00:00
Tiago Mück
027b508a38 mem-ruby: fix missing transition in CHI-mem
JIRA: https://gem5.atlassian.net/browse/GEM5-1195

Change-Id: I0aae4b9042cb6565c77cc8781b514a9e65ab161b
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63676
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-09-28 18:56:04 +00:00
Tiago Mück
c6a460eff4 mem-ruby: fix CHI memory controller
Break up the transition to READING_MEM into two separate steps so
contention at the requestToMemory queue won't block the TBE
initialization.

JIRA: https://gem5.atlassian.net/browse/GEM5-1195

Change-Id: Ifa0ee589bde67eb30e7c0b315ff41f22b61e8db7
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63675
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-09-28 18:56:04 +00:00
Tiago Mück
3871f57dc3 configs: set requestToMemory buffer size for CHI
Currently TBEs for write requests are deallocated when the request is
pushed to memory, so an unlimited requestToMemory buffers size allows
for an unlimited number of outstanding write requests.

Set the requestToMemory buffers size prevents this.
The buffer size should be greater than the enqueue latency to allow at
least one enqueue per cycle.

JIRA: https://gem5.atlassian.net/browse/GEM5-1195

Change-Id: I31829b6bbabd8b45e1142790038c27bd459fa709
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63674
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-09-28 18:56:04 +00:00
Tiago Mück
06a8a47322 configs: fix CHI mem buffers
Disabling randomization for the memory request and response buffers.
CHI requires that memory responses for the same address arrive in
the same order the request was sent.

Change-Id: Ia4236188679beaf2969978675414a870ccd9f94a
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63673
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-09-28 18:56:04 +00:00
Tiago Mück
ba3aa067a3 configs: CHI inc transitions_per_cycle
Previous limit may unintentionally throttle performance for controllers
with a large TBE table and high traffic.

Change-Id: I34d6f8727519b259bb3d4a80b1fff6c59197c508
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63672
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-09-28 18:56:04 +00:00