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Author SHA1 Message Date
Yu-hsin Wang
1f713320fe dev: Expose ResetRequestPort constructor 
Port::Port is in protected scope. ResetRequestPort should expose the
constructor by itself.

Change-Id: I72ce701fca89379f90e212d7411f481ae1e1977a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59209
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
 2022-04-29 02:42:54 +00:00
Bobby R. Bruce
d5da783d75 util: Remove util/stats directory 
This does not appear to be used, we are therefore removing it.

Change-Id: I7c99f2e9879efc467bb75e279c4ef3b92fb1aa68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47025
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-28 20:53:42 +00:00
Kaustav Goswami
fda07590df cpu: nullptr in a DPRINTF statement 
This change fixes the crashing of gem5 when `Branch` debug flag
is enabled. A DPRINTF statement had a nullptr. This change
prints `INVALID_TARGET` if the nullptr is encountered.

Signed-off-by: Kaustav Goswami <kggoswami@ucdavis.edu>
Change-Id: I40bd42c07de25a493a3dd1094a2fd8cc0ce0a79b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59109
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2022-04-28 16:57:59 +00:00
Giacomo Travaglini
f8589a4719 sim, arch-riscv: Remove Fault debug flag 
There is already a Faults debug flag used by Arm and X86 so
having both Fault and Faults is highly confusing

Change-Id: Id5c17f19b51c6257dfc470d07ba050a9de7a9db3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59152
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-04-28 08:52:49 +00:00
Gabe Black
695c8b7f49 cpu-minor: Use the InvalidRegClass to track invalid RegIds. 
Use that instead of the zero register. This avoids two assumptions,
first that there is a zero register in the first place, and second that
the zero register is an integer.

It also avoids referring to the IntRegClass in non-ISA specific code.
It's very likely that all ISAs will have integer registers, but we
should not build in assumptions about what types of registers an ISA has
in general. For instance, not all ISAs have vector predicate registers,
or a scalar floating point register file.

Change-Id: I730fec90f42b90b5be7e1baddf896e18c53e8510
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49711
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-04-27 20:27:22 +00:00
Jason Lowe-Power
1e9db5b9cf python: Add error for creating abstact SimObjects 
Currently, if you try to instantiate an abstract SimObject the error is
confusing and unhelpful.

"TypeError: _m5.param_<type>.<type>Params: No constructor defined!"

Now, it will instead say "Cannot instantiate an abstract SimObject"
and include the name of the object that causes the error.

Change-Id: Ia8c51e29dccd999ec90dcd39710cc91d9a5fb86f
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59049
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-27 16:56:08 +00:00
Bobby R. Bruce
7f25e7acbf stdlib: Fix race condition in creating of resource dir 
Found via a failing weekly test:
https://jenkins.gem5.org/job/weekly/46/

The following exception was thrown:

```
FileExistsError: [Errno 17] File exists: '/nobackup/jenkins/workspace/weekly/tests/gem5/resources'

At:
  /usr/lib/python3.8/os.py(228): makedirs
  build/GCN3_X86/python/gem5/resources/resource.py(156): __init__
  /nobackup/jenkins/workspace/weekly/tests/gem5/configs/x86_boot_exit_run.py(192): <module>
  build/GCN3_X86/python/m5/main.py(440): main
```

It was found that, in cases where the resource directory does not exist,
there is a race condition between gem5 threads to create the directory.
This patch fixes this so threads that lose this race continue normally.

Change-Id: Ie3323c4df0b247e7830c5d3ab93a4d7f9224fe36
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59090
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-26 19:14:34 +00:00
Bobby R. Bruce
bcabf189fb tests,gpu-compute,mem-ruby: Add GPU Ruby random test 
This adds the GPU protocol random tester to the quick/Kokoro tests. The
input has been sized to take around 20 seconds and provides good
coverage for the coherence protocol.

This test can be run with the following:

```
cd tests
./main.py run -j`nproc` gem5/gpu
```

Change-Id: I08d199f0de8cca985f992b7f39b5f82e4218c82d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58270
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2022-04-26 19:14:22 +00:00
Bobby R. Bruce
33281840ff tests,gpu-compute: Replace gcn3 tests with vega testlib tests 
Any X86 quick tests were set to use GCN3_86. This was to minimize the
number of gem5 targets to build during the quick tests. Since the
introduction of VEGA, we wish to test VEGA during the quick tests. As
such, this patch will replace all GCN3_X86 tests with VEGA_X86 tests.

Change-Id: Ibdd7832e43a284936db5102d41161388bc721bd1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59012
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-26 19:14:22 +00:00
Bobby R. Bruce
e3fc3694a1 learning-gem5,tests: Fix 'valid_isas' in learning gem5 part 3 
This was set to 'gcn3_x86_tag'. We only do this for quick X86 tests (to
minimize the build targets during the quick tests). This is not
necessary for the long tests.

Change-Id: I3bd20b53e04d129462e6f62a24f34b093f4a1b80
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59011
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-26 19:14:22 +00:00
Bobby R. Bruce
592e00efdd tests: Add the 'vega_x86_tag' to testlib 
This allows us to test ./build/VEGA_X86/gem5.opt targets.

Change-Id: I4d8309f928317d03b63e07e5ebb43de68cded9f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59010
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
 2022-04-26 19:14:22 +00:00
Yu-hsin Wang
9e4c5537a4 fastmodel: Add CortexR52 model reset port 
The model reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I15101bfe11dee40b63cc29c2befb610beb3d32aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58813
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-26 06:31:51 +00:00
Yu-hsin Wang
b4d924fdca fastmodel: Add CortexA76 model reset port 
The model reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I9aacc398b299e26e4675f7229db1afc8f6c8a34f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58814
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-26 06:31:51 +00:00
Yu-hsin Wang
8df2ebf43e dev: Add a special reset interface to consolidate reset logic 
How to reset a model correctly is very different between models. Take
cpu models for instance, they have different reset pins for different
parts(typically one for each core, one for shared component, one for
debug interface). To make users more easily to reset the model, here we
want to introduce a special reset port. By implementing the port, users
can simply request a whole reset to the model. If users want to do
partial resets, users still can access the raw pins to achieve what they
want.

Change-Id: I746121d16441e021dc3392aeae1a6d9fa33d637a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58810
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-26 06:31:51 +00:00
Matthew Poremba
adef87fb27 configs: Make vega10_kvm.py runnable 
The current script is echoing the command instead of running it (oops).
Also change the dmesg level to 3 to hide warnings from console output.
Level 8 should really only be used when debugging.

Change-Id: I90937ef13bf598cef1f58af69da1fdc9038d1e37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59052
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-23 01:21:14 +00:00
Matthew Poremba
fa808ae7e0 util: Add dockerfile for building GPUFS application 
In order to compile binaries to run in GPUFS, users would either have to
install ROCm 4.2 locally, use something like docker, or build within
gem5 using KVM and copy the binary out. The simplest way of those is to
use docker. This minimal dockerfile contains only ROCm 4.2 and can build
binaries that will be placed on the host which can be run in gem5.

For example, current gem5-resources can be built for gem5 as follows:

cd util/dockerfiles/gpu-fs
docker build -t rocm42-build .
cd /path/to/gem5-resources/src/gpu/hip-samples
docker run --rm -u $UID:$GID -v ${PWD}:${PWD} \
    -w ${PWD} rocm42-build make

Those binaries can then be run in gem5 using the
configs/example/gpufs/vega10_kvm.py script:

build/VEGA_X86/gem5.opt configs/example/gpufs/vega10_kvm.py --app \
    /path/to/gem5-resources/src/gpu/hip-samples/bin/MatrixTranspose

Change-Id: Ie76146be0ccf6fcc1941322cacc15965fe70073a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59051
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-23 01:21:14 +00:00
Samuel Stark
52743eb975 mem-ruby: Support for unaddressed mem requests in the Sequencer 
JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I66f7779f447d56e72e1b1f1ca2b84f1b50057542
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57294
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-22 08:55:10 +00:00
Matthew Poremba
8a53add7f8 dev-amdgpu: Fix frame writes for <32-bit writes 
In theory a packet between one and eight bytes can be written to frame
buffer memory from the driver. In gem5 pkt->getLE<utin32_t>() will
assert if the packet size is <32-bits. Change to pkt->getUintX(...) to
fix this issue.

Change-Id: If8554013e4ea7bac90985487991d0bf8bdc765ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58852
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-21 21:32:53 +00:00
zhongchengyong
29a39d9472 arch-riscv: RISCV call/ret instructions aren't decoded correctly 
This change adds IsReturn and IsCall flag for RISC-V jump instructions
by define new "JumpConstructor" in standard.isa, and fixes target
overwriting in buildRetPC.

See RAS presentation in spec:
Section 2.5 Page 22 of https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
Or:
https://github.com/riscv/riscv-isa-manual/blob/master/src/rv32.tex#:~:text=Return%2Daddress%20prediction,%5Cend%7Btable%7D

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1139

Change-Id: I9728757c9f3f81bd498a0ba04664a003dbded3bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58209
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-21 06:34:40 +00:00
Sungkeun Kim
af534729c4 mem-garnet: Packet Tracing of garnet network 
This is a patch to keep track of
a single packet in the garnet network.
This patch would help for finding a deadlock issue
during the extending the garnet network.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1181

Change-Id: I1138484807ef127a3240b46154e29ae77678f1e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58857
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-21 01:23:24 +00:00
Iru Cai
cbd401ebc4 util: fix the cxx_config example 
This change replaces and removes the out-of-date APIs to fix the build
error, and add fixClockFrequency() call to fix the runtime error. We
also need the TRACING_ON macro and C++17 to build because of the
header changes.

Tested with X86 and tests/test-progs/hello. Checkpoint restore is not
tested yet.

Change-Id: Id92bb7954defea15b026eba3229a453b688929be
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58989
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-20 06:07:09 +00:00
Bobby R. Bruce
74f3f190fb stdlib: Add tar unpacking to downloader 
With this commit gem5-resources can exist as tarballs to be unpacked
after download. This requires the field "is_tar_archive : true" to be
present in the resource description in resources.json.

Change-Id: Ia835c1777425a5aafe8ba7ee9c725edf6d45f68c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58851
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-19 22:01:00 +00:00
Bobby R. Bruce
a64c8a9fb1 util,stdlib: Add util/md5.py 
This is a useful script for quickly checking the hash values of
resources. Since this uses the same function as the downloader, using
this utility ensures the values are identical to that found in
resources.json (i.e., what the downloader checks against to see if a
resource has changed).

Change-Id: I37f39cb8fd2c92725d956170b3656cbfb4480ce6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58850
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-19 22:01:00 +00:00
Bobby R. Bruce
e33f9b830b stdlib: Update the stdlib resource's md5 utils 
The commit does the following:

- Moves the md5 functions to their own Python module (this will allow us
to use this elsewhere).
- Add functionality to enable md5 values for directories.
- Adds Pyunit tests for the md5 functionality.

Change-Id: I224d4584ed6c35fac3a75e221b3cb48d863ffa6f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58849
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2022-04-19 22:01:00 +00:00
Bobby R. Bruce
35f7008602 tests: Fix 'valid_hosts' field for KVM tests 
In some cases where we wish to use X86 KVM the 'valid_hosts' field was
set to 'constants.supported_hosts'. This can cause problems as the only
valid host for an X86 KVM test is X86. This patch fixes this.

This fix will likely fix some flakey errors observed in the Nightly
tests.

Change-Id: Id0a906ca6602c0358ae632cce314769807bf6e07
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58970
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-19 19:08:30 +00:00
Gabe Black
6d8a5ad2ad stdlib: Add missing ()s in get_supported_isas. 
A function was used directly instead of being called when interating
through ISA names.

Change-Id: I9dc53259a766a68070e0b79bb55f721a93fcdeed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58929
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-17 01:07:55 +00:00
Hoa Nguyen
17d945b698 configs: Fix the command in the comment of arm-hello.py 
Change-Id: I5e020e066c0f6792077fbf2ef65b7f90bb9c37f9
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58830
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-16 18:22:01 +00:00
GWDx
1680d7dab4 configs: Fix spelling mistakes. 
Replace "fequency" to "frequency".

Change-Id: I307c8b6d8e60cfcb213f22aca3f6abd43c6b5b1e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58229
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-16 11:58:40 +00:00
Hoa Nguyen
e32de65973 stdlib, configs: Fix riscv-ubuntu-run error 
This change,
https://gem5-review.googlesource.com/c/public/gem5/+/58790,
mistakenly constructs the root object outside of the
Simulator object, which would create another Root object.

The correct usage of a Simulator object is to pass the board to
the object without defining the root.

Change-Id: Iaa9aabe058a00abd964bf935b1b3f05456713275
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58889
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-15 04:20:01 +00:00
Jerin Joy
70fd98e807 arch-riscv: Added the Zbs bitmanip instructions 
Added the bclr, bclri, bext, bexti, binv, binvi, bset, bseti
instructions.

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I126d659d973b250b642bd56b3b149f0ee6a3323e
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58632
Reviewed-by: Luming Wang <wlm199558@126.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2022-04-13 20:09:59 +00:00
Jerin Joy
df886bc8c1 arch-riscv: Added the Zbc bitmanip instructions 
Added clmul, clmulh, clmulr instructions.

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I98dc76ddde052f56e32eabed12af87039def665b
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58631
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Luming Wang <wlm199558@126.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-13 20:09:59 +00:00
Jerin Joy
aee1622a6c arch-riscv: Added the Zba and Zbb bitmanip instructions 
Zba instructions added:
add.uw, sh1add, sh1add.uw, sh2add, sh2add.uw, sh3add, sh3add.uw, slli.uw

Zbb instructions added:
andn, orn, xnor, clz, clzw, ctz, ctzw, cpop, cpopw, max, maxu, min,
minu, sext.b, sext.h, zext.h, rol, rolw, ror, rori, roriw, rorw, orc.b, rev8

Changes based on spec:
https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0.pdf

Change-Id: I056719f62eee89e0f085d1bf1fa182f9dfe614d8
Signed-off-by: Jerin Joy <joy@rivosinc.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58630
Reviewed-by: Luming Wang <wlm199558@126.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-13 20:09:59 +00:00
Yu-hsin Wang
72255064d6 fastmodel: Export more CortexR52 reset pin 
Change-Id: I20f34ae2061e886b35fe9439dbb8e25ce3571e4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58811
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-13 08:44:03 +00:00
Yu-hsin Wang
9dce95844a fastmodel: Export more CortexA76 reset pin 
Change-Id: I386cf659fa77b2005f808fde51ef772ac0a57735
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58812
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-13 08:44:03 +00:00
Gabe Black
7392cd470e scons: Ensure the fast model license count is always at least 1. 
Even though the default value for the license count is 1, it seems that
if fast model is disabled, kconfig will set it to 0. When creating a
cycle using itertools over a list with zero elements, it will raise a
StopIteration.

Even though we don't actually try to build any fast model components
in that case, we do still set them up with a license slot. If the
cycle iterator is essentially broken, that will prevent that from
working and break the build.

This change forces the license count to be at least 1, even if fast
model is disabled and the license count may be set to 0 in the config.

Change-Id: Ia8df256a8f292deb6fb6fa3c5f9a7d58c2b7f782
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58490
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-13 02:16:13 +00:00
Yu-hsin Wang
7a8af170e3 scons: Fix script failed when default files not found 
Change-Id: Ic673783cb5050159a141a869ca17b1ac09a924ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58809
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-13 01:11:36 +00:00
Gabe Black
7cc384c308 arch: Eliminate the now unused read_code and write_code args. 
Also eliminate the buildReadCode and buildWriteCode methods.

Change-Id: I27b1b87ab51a44b5d7280e29e22f38d97d968a65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49743
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-12 23:50:52 +00:00
Gabe Black
cfe3ed47a6 arch-x86: Override make(Read|Write) instead of (read|write)_code. 
Change-Id: Iab077f58e19aa6bfeed555caa31a4c8b3d261059
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49741
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2022-04-12 23:50:38 +00:00
Jason Lowe-Power
4978bf8d5a scons: Fix bug in error message 
The variable p doesn't exist in the context. Just remove the extra
print. Even without the specific variable printed the error message is
pretty helpful.

Change-Id: If681d686c228c1362b8cc46cb14a94d7302f3793
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58429
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-12 20:30:54 +00:00
Hoa Nguyen
00fd640662 stdlib, configs: Migrate riscv-ubuntu-run example to Simulator 
Change-Id: Ie08fcf46139871bc98b9bf783d0b4d9913eace3e
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58790
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-12 18:44:35 +00:00
Bobby R. Bruce
f6b1f3f850 tests: Disable failing 8-core Boot Tests for Timing/Atomic 
As noted here: https://gem5.atlassian.net/browse/GEM5-1217, the Atomic
and Timing Core systems are not working with 8 cores when run with a
classic or MI_example cache heirarchy. Until the root cause of this
issue can be determined. These tests are being disabled.

Change-Id: Ia19579029bd20c57cca8d225068d17c4b29f1773
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58770
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-04-12 18:08:10 +00:00
Bobby R. Bruce
06881ae2a5 tests: Disable failing MI_Example/Timing CPU X86 Boot Tests 
As noted in this jira issue:
https://gem5.atlassian.net/browse/GEM5-1216, these tests are failing.
We are going to disable them until we can figure out the root cause of
this problem.

Change-Id: I8511beaac0bae3c6d2a42af59035cc4620cd5bb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58769
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-04-12 18:08:10 +00:00
Tiago Mück
eb0b4ba657 mem-ruby: CHI fix for WUs on local+upstream line 
Fix for WriteUnique operations on cache lines that are both local and
upstream

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I99def32948d3f0ced9cfc7f7712a0f4ae9aab0cd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57299
Reviewed-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-12 10:21:57 +00:00
Gabe Black
bb45503c5f misc: Add KCONFIG.md file which talks about Kconfig files. 
There are some minor aspects about how Kconfig files are used in gem5
which are a little different from how they are documented online or are
used in other projects. Document that in this file.

Change-Id: Ib981d1e265cf466d453071b33820d6baa24e17d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58634
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-12 04:23:40 +00:00
Matthew Poremba
b64467025d arch-vega: Implement SOP2 S_MUL_HI instructions 
Two new 32-bit signed and unsigned variants of S_MUL were added in
gfx900 which operate similar to S_MUL expect they shift the product by
32 bits after multiplication. Tested with Histogram HIP-Sample and
b+tree in rodinia 3.0 HIP port.

Change-Id: I1bed32b17ccda7aa47f3b59528eb3304912d3610
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58473
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-11 17:06:43 +00:00
Samuel Stark
7e84a14a26 mem-ruby: AbstractController unaddressed profiling 
Adds support for profiling "unaddressed" transactions,
which are associated with a unique ID rather than a memory address,
to AbstractController.

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: Ib75f3f38dc4910acc2ad4f1c7bf88c9193568203
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57297
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-11 09:57:43 +00:00
Samuel Stark
920859e191 mem-ruby: Added upstream_nodes to AbstractController 
Added support for an upstream_nodes NetAddr list in AbstractController,
which will be used in future CHI work.

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I30a6d621d7f201d89f0b13dab8ed4dd1f1f6caa3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57296
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-11 09:57:43 +00:00
Samuel Stark
65f8bf4460 mem-ruby: Support for unaddressed mem requests in the RubyRequest 
JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I5aa44186888b95f81bec524ff57e8dbf4c9166f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57293
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-11 07:31:34 +00:00
Samuel Stark
32ed7794d8 mem-ruby: Add TLBI callbacks to the RubyPort 
JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I984fd497b7209772106150abb853c91c3d818dfd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57295
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-11 07:31:34 +00:00
Samuel Stark
6dac25a7f4 cpu: Handle external TLBI Sync requests in O3CPU 
JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I02e55a42e0f717211b481e65d59900fc3d05f061
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57292
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-04-11 07:31:34 +00:00