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mem-ruby: Added upstream_nodes to AbstractController

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Added support for an upstream_nodes NetAddr list in AbstractController,
which will be used in future CHI work.

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I30a6d621d7f201d89f0b13dab8ed4dd1f1f6caa3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57296
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Samuel Stark
2021-09-22 14:09:45 +01:00
committed by Giacomo Travaglini
parent 65f8bf4460
commit 920859e191
3 changed files with 15 additions and 2 deletions
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8
src/mem/ruby/slicc_interface/AbstractController.cc
View File

@@ -108,7 +108,13 @@ AbstractController::init()
}
downstreamDestinations.add(mid);
}
// Initialize the addr->upstream machine list.
// We do not need to map address -> upstream machine,
// so we don't examine the address ranges
upstreamDestinations.resize();
for (auto abs_cntrl : params().upstream_destinations) {
upstreamDestinations.add(abs_cntrl->getMachineID());
}
}
void

5
src/mem/ruby/slicc_interface/AbstractController.hh
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@@ -214,8 +214,12 @@ class AbstractController : public ClockedObject, public Consumer
MachineID mapAddressToDownstreamMachine(Addr addr,
MachineType mtype = MachineType_NUM) const;
/** List of downstream destinations (towards memory) */
const NetDest& allDownstreamDest() const { return downstreamDestinations; }
/** List of upstream destinations (towards the CPU) */
const NetDest& allUpstreamDest() const { return upstreamDestinations; }
protected:
//! Profiles original cache requests including PUTs
void profileRequest(const std::string &request);
@@ -375,6 +379,7 @@ class AbstractController : public ClockedObject, public Consumer
AddrRangeMap<AddrMapEntry, 3> downstreamAddrMap;
NetDest downstreamDestinations;
NetDest upstreamDestinations;
public:
struct ControllerStats : public statistics::Group

4
src/mem/ruby/slicc_interface/Controller.py
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2017,2019,2020 ARM Limited
# Copyright (c) 2017,2019-2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -75,5 +75,7 @@ class RubyController(ClockedObject):
# These can be used by a protocol to enable reuse of the same machine
# types to model different levels of the cache hierarchy
upstream_destinations = VectorParam.RubyController([],
"Possible destinations for requests sent towards the CPU")
downstream_destinations = VectorParam.RubyController([],
"Possible destinations for requests sent towards memory")