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mem-ruby: CHI fix for WUs on local+upstream line

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Fix for WriteUnique operations on cache lines that are both local and
upstream

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I99def32948d3f0ced9cfc7f7712a0f4ae9aab0cd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57299
Reviewed-by: Tiago Muck <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Tiago Mück
2021-09-22 14:05:28 +01:00
committed by Giacomo Travaglini
parent bb45503c5f
commit eb0b4ba657
1 changed files with 11 additions and 1 deletions
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12
src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
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@@ -337,7 +337,7 @@ transition({I, SC, UC, SD, UD, RU, RSC, RSD, RUSD, RUSC,
// WriteUniquePtl
transition({UD,UD_RU,UD_RSD,UD_RSC,UC,UC_RU,UC_RSC},
transition({UD,UD_RSD,UD_RSC,UC,UC_RSC},
{WriteUnique, WriteUniquePtl_PoC, WriteUniqueFull_PoC, WriteUniqueFull_PoC_Alloc},
BUSY_BLKD) {
Initiate_Request;
@@ -347,6 +347,16 @@ transition({UD,UD_RU,UD_RSD,UD_RSC,UC,UC_RU,UC_RSC},
ProcessNextState;
}
transition({UD_RU,UC_RU},
{WriteUnique, WriteUniquePtl_PoC, WriteUniqueFull_PoC, WriteUniqueFull_PoC_Alloc},
BUSY_BLKD) {
Initiate_Request;
Initiate_WriteUnique_LocalWrite;
Profile_Miss;
Pop_ReqRdyQueue;
ProcessNextState;
}
transition({SD, SD_RSD, SD_RSC, SC, SC_RSC},
{WriteUniquePtl_PoC, WriteUniqueFull_PoC, WriteUniqueFull_PoC_Alloc},
BUSY_BLKD) {