stdlib, configs: Migrate riscv-ubuntu-run example to Simulator
Change-Id: Ie08fcf46139871bc98b9bf783d0b4d9913eace3e Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58790 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
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@@ -53,6 +53,7 @@ from gem5.components.processors.cpu_types import CPUTypes
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from gem5.isas import ISA
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from gem5.coherence_protocol import CoherenceProtocol
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from gem5.resources.resource import Resource
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from gem5.simulate.simulator import Simulator
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# This runs a check to ensure the gem5 binary is compiled for RISCV.
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@@ -116,32 +117,5 @@ board.set_kernel_disk_workload(
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root = Root(full_system=True, system=board)
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m5.instantiate()
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# We simulate the system till we encounter `m5_exit instruction encountered`.
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exit_event = m5.simulate()
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# We check whether the simulation ended with `m5_exit instruction encountered`
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if exit_event.getCause() == "m5_exit instruction encountered":
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# We acknowledge the user that the boot was successful.
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print("Successfully completed booting!")
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else:
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# `m5_exit instruction encountered` was never encountered. We exit the
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# program unsuccessfully.
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print("The startup was not completed successfully!",)
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print(
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"Exiting @ tick {} because {}."\
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.format(m5.curTick(), exit_event.getCause())
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)
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exit(-1)
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# We are done with the simulation. We exit the program now.
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print(
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"Exiting @ tick {} because {}."\
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.format(m5.curTick(), exit_event.getCause())
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)
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simulator = Simulator(board=board)
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simulator.run()
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